Performance Evaluation of Digital Comparator Using Different Logic Styles

Abstract

In the present scenario, low power, speed, and size play a significant role specifically in the field of digital VLSI circuits. The major goal of this paper is to design and implement a digital comparator using different logic techniques to compare power consumption, propagation delay, and transistor count. The results of this paper are simulated on the EDA tanner tool realized in 45-nanometer technology at 0.7 v supply voltage.

KEYWORDS:

• Digital comparator
• Half adder logic technique
• Power dissipation
• Propagation delay
• Transmission gate logic technique
• Transistor count

ACKNOWLEDGEMENT

The authors like to thank the faculties of ECE Dept, Bankura Unnayani Institute of Engineering for useful advices.

DISCLOSURE STATEMENT

No potential conflict of interest was reported by the authors.

Additional information

Notes on contributors

Dwip Narayan Mukherjee

Dwip Narayan Mukherjee had been awarded MTech degree in ECE from Burdwan University, Burdwan, India. He is currently working as an assistant professor in Electronics and Communication Engineering Department of Bankura Unnayani Institute of Engineering, West Bengal, India. Research interests include in the area of VLSI low power design, image processing, and signal processing.

Corresponding author. E-mail: [email protected]

Saradindu Panda

Saradindu Panda is currently serving as the HOD of Electronics and Communication Engineering Department of Narula Institute of Technology, Agarpara, Kolkata since nine years. He has received PhD degree in ECE from NIT, Durgapur in 2014. He has received his BE degree in ECE from UIT, Burdwan University in 2004 and MTech degree in VLSI and microelectronics technology from Jadavpur University in 2007. He is also a National Scholarship winner in his school level. He is a professional member of IEEE, professional member of IET, institutional member of IETE. His research interests include low power and high speed VLSI circuit design, noise modelling and analysis of advanced semiconductor devices like DGMOSFET, SGMOSFET, MESFET, HEMT, etc., design of SOCs, VLSI signal processing, advanced digital system design, and embedded system design. He has published one book on microelectronics and optoelectronic devices and more than 30 research articles in peer-reviewed international journals, national and international conferences.

E-mail: [email protected]

Bansibadan Maji

Bansibadan Maji is now a senior professor of ECE Department in NIT, Durgapur, West Bengal, India. He is now the Head of the Department of ECE at NIT. His main research areas are on microwave, antenna, VLSI design and low power device, and circuits. He has more than 56 publications in different international and national journals and conference proceedings. He has published more than 50 research articles in peer-reviewed international journals, national and international conferences.

E-mail: [email protected]