Aggressive Packet Combining Scheme with Packet Reversed and Packet Shifted Copies for Improved Performance

Abstract

Wireless channel suffers from high bit error rate due to noise, fading, interference, and shadowing. High bit error rate significantly reduces the effective bandwidth available to users thus affecting the overall throughput. In order to tackle high bit error rate and multiple bit errors with low latency (for fast delivery), a new modification of APC scheme is proposed in this paper. In the proposed scheme, first copy sent from transmitter to receiver is an exact replica of the original packet; if this transmission is unsuccessful, the transmitter retransmits two copies of the original packet in which one of the retransmitted copy is bit reversed of the original packet and the other retransmitted copy is bit shifted copy of the original packet. The proposed aggressive packet combining scheme with packet reversed packet shifted copies has been studied analytically and by simulation in MATLAB. The analytical results show that the proposed packet reversed packet shifted aggressive packet combining scheme can correct multiple bit errors (random errors and burst errors) even when the errors occur in the same bit locations of all received erroneous copies, yielding better error correction capability and throughput than existing packet combining schemes.

KEYWORDS:

• Aggressive packet combining
• Backward error correction
• Bit error rate
• Forward error correction
• Packet combining
• Throughput

ACKNOWLEDGEMENTS

We would like to thank Prof. Dr. C.T. Bhunia for his continuous support and guidance. Also, we would like to thank NIT Arunachal Pradesh, where we could have the environment to carry out this work.

DISCLOSURE STATEMENT

No potential conflict of interest was reported by the authors.

Additional information

Notes on contributors

Yang Saring

Yang Saring has an over five years of industrial experience as lead engineer at Samsung India Software Operations, and is now serving as an assistant professor at National Institute of Technology Arunachal Pradesh in the department of Electronics and Communication Engineering. Her areas of interest include signal processing, error control techniques.

Corresponding author. E-mail: [email protected]; [email protected]

Shashank Vikram Singh

Shashank Vikram Singh is a MTech student in National Institute of Technology Arunachal Pradesh in the department of Electronics and Communication Engineering. His areas of interest include wireless communication and Information Technology

E-mail: [email protected]