Modeling and Fabrication Aspects of Cu- and Carbon Nanotube-Based Through-Silicon Vias

ABSTRACT

This paper discourses the variations in methods of fabrication and modeling of Through-Silicon Vias (TSVs) in chronological order. Three-dimensional (3D) integration is an emerging technology that forms multi-functioning high-performance ICs by vertically stacking of disparate technologies and components altogether. TSV has the potential to become an essential component in integration and packaging of 3D ICs. However, the limited information about TSV technologies brings the challenge in selecting the appropriate filler material of TSVs. This review paper overviews the copper (Cu)- and carbon nanotube (CNT)-based TSVs and their pros and cons to be established as suitable filler material for 3D TSVs. The equivalent electrical models of both Cu and CNT-based TSVs are discussed addressing their advantages and disadvantage to reason out the most promising method for the modeling of TSVs.

KEYWORDS:

• Carbon nano tubes
• RLCG model
• single-walled carbon nanotube (SWCNT) TSV models
• through-silicon vias (TSVs)

ORCID

Brajesh Kumar Kaushik http://orcid.org/0000-0002-6414-0032

Additional information

Notes on contributors

Tanu Goyal

Tanu Goyal awarded her M.Tech in VLSI Design at Banasthali Vidyapith, Rajasthan, India. Currently she is associated with the academic and administrative activities in Electronics and Communication Engineering Department in IEC Group of Institutions, Greater Noida, India.

Her current research interest is signal integrity, carbon nano tubes and through silicon vias.

Manoj Kumar Majumder

Manoj Kumar Majumder awarded his PhD in Microelectronics and VLSI group at Indian Institute of Technology, Roorkee, India. Currently he is associated with the academic and administrative activities in Electronics and Communication Engineering department in IIIT Naya Raipur, Chattisgarh, India.

His current research interest is Carbon Nanotube and Graphene nanoribbon based VLSI interconnects and vias. Email: [email protected]

Brajesh Kumar Kaushik

Brajesh Kumar Kaushik received his Ph.D. in 2007 from Indian Institute of Technology, Roorkee. In 1998, he joined as a lecturer at G. B. Pant Engineering College Pauri, Garhwal, where he served as Assistant Professor till 2009. He is currently with the Department of Electronics and Communication Engineering, Indian Institute of Technology Roorkee, India.

His current research area includes Electronic simulation, Low power VLSI Design. He has published more than 150 research papers in various international journals and conferences. He has received many awards and recognitions from IBC, Cambridge such as top 100 scientists in World- 2008 and International Educator of 2008. Email: [email protected]