Analysis of Extended Pile Gate Trapezoidal Bulk FinFET

Abstract

With technology scaling, innovative approaches in the device design are increasingly being explored. Improving device design is one of the focus areas for meeting the demand for low power high-speed circuit design. FinFET being the most promising device structure within the nanoscale regime, different structure variants of FinFET have been proposed and successfully implemented. In this paper, bulk FinFET device design is modified with a new design approach. Two different Si bulk trapezoidal FinFET devices, one with stacked gate and another with extended stacked gate are implemented using the 3D TCAD tool. The improvement in the performance metrics is denoted after comparing it with a simple trapezoidal Bulk FinFET device. Investigated performance metrics include subthreshold slope, Drain-Induced Barrier Lowering, Leakage Current, transconductance generation factor and threshold voltage and internal capacitance across Gate-Substrate, Gate-Drain and Gate -Source terminals of the device.

KEYWORDS:

• DIBL – drain-induced barrier lowering
• SS – subthreshold slope
• SOI – silicon-on-insulator
• FD-SOI – fully depleted silicon-on-insulator
• GAA – gate all around

ACKNOWLEDGEMENT

Corresponding author would like to thank Mr Amit Saini from Cadre Design System for software support.

Additional information

Notes on contributors

Sangeeta Mangesh

Sangeeta Mangesh is a faculty in Department of Electronics Engineering, JSS Academy of Technical Education, Sector-62, Noida. She has been associated with teaching undergraduate and postgraduate engineering courses for more than 15 years. Presently, she is pursuing her PhD in the field of microelectronics from Dr APJ Abdul Kalam Technical University Lucknow.

P.K. Chopra

Pradeep Kumar Chopra entered the field of education in the year 2004 after 24 years of exemplary service in the technical branch of the Indian Air Force. For his exemplary services, he was awarded ‘Vishisht Sava Medal’ by the President of India for engineering skills of highest order in the year 1993. After taking voluntary retirement from the IAF in the year 2004 and entered the field of education. He completed his PhD in the field of ‘electronics & communication engineering’ from the prestigious G G S I P University, New Delhi. Presently, he is the Dean and Head of Department of Electronics & Communication Engineering and Electronics & Instrumentation Engineering. He has published more than 25 papers in reputed journals and conferences. He is Fellow of Institution of Electronics & Telecommunication Engineers, New Delhi. He is also an expert of National Board of Accreditation (NBA) in new system of outcome-based education under Washington accord for Tier-I and Tier-II. Inspect Engineering colleges for NBA accreditation for UG/ PG engineering courses as specialist member of NBA accreditation team. Email: [email protected]

K.K. Saini

Krishan K Saini is PhD in physics from Delhi university. He has served for more than 34 years as chief scientist in National Physical Laboratories, New Delhi. He has also served as guest faculty for teaching post graduate engineering course in CDAC Noida and JSSATE Noida. He has published 32 papers in SCI journals and more than 50 in internationally organized conference symposia. Technology developed under his leadership reported to FICCII for Scratch Resistant photoactive TiO2 coatings on large area Glass substrates in 2010 was selected among the top 50 technologies in the country. Email: [email protected]