Corrigendum

This article refers to:

Design of CNTFET-based Current-mode Multi-input m:3 (4 ≤ m ≤ 7) Counters

Article title: Design of CNTFET-based Parallel Multipliers using Cur-rent-Mode Multi-Input m: 3 (4≤m≤7) Counters

Authors: Mohammad Hassan Bagheri, Mehdi Bagherizadeh, Mona Moradi & Mohammad Hossein Moaiyeri

Journal: IETE Journal of Research

DOI: https://doi.org/10.1080/03772063.2018.1553640

The data in Table 3 were inserted in incorrect columns.

Corrected Table 3 (furnished below) has been published in the updated version.

Table 3. Comparison of the second proposed CML 4:3 counter architecture.

Design	Delay (ps)	Power (µW)	PDP (fJ)
[16]	32.22	24.30	0.78
[4]	30.32	23.17	0.70
Proposed	20.24	20.32	0.41