Extraction and Analysis of Gate Leakage Current Mechanism in Silicon Carbide (SiC) MIS Capacitors

Abstract

Wide bandgap and resulting low intrinsic carrier concentration enable longer charge retention time and high-temperature operation of Silicon carbide (SiC) flash memory devices. However, charge leakage through gate oxide reduces memory retention time and reliability of gate dielectric. Knowledge of conduction mechanisms of gate leakage current is essential for the optimization of process conditions to reduce leakage current and determination of suitable operating voltage of flash memory devices. In this work, conduction mechanisms contributing to gate leakage current in SiC MIS capacitors with different gate dielectric are extracted for the entire range of the gate electric field. Space charge limited (SCL) conduction mechanisms either Ohm’s law or trap filled limit process or combination of both are observed to be dominant at the low electric field. Hopping conduction found to be dominating the leakage current when the slope of leakage current changes from the lower value to a higher value. The sequence of mechanisms contributing to gate leakage current from low electric field to high electric field is found to be same in SiO₂ annealed in O₂ and N₂, SiON and Al₂O₃/SiON stack. The trap filled limit process, trap-assisted tunneling and FN tunneling are dominating the gate leakage current at low, mid and high electric field respectively in all the investigated MIS capacitors.

Keywords:

• Gate leakage current
• High-κ dielectric
• MIS capacitors
• SiC
• Space charge limited conduction
• Trap-assisted tunneling and FN tunneling

Additional information

Notes on contributors

Papanasam Esakki

P Esakki is working as an assistant professor at SASTRA deemed university since June 2017. He completed his BE degree in electronics and communication engineering from Manonmaniam Sundaranar University, Tamil Nadu and ME degree in VLSI design from Anna University Chennai. He completed his Ph.D. degree in electronics from IIITDM Kancheepuram in 2017. He published in 2 international journals and his research work was presented in two international conferences. His research interest includes alternate substrate MIS/MOS devices and VLSI design Email: [email protected]

Binsu J. Kailath

Binsu J Kailath is an associate professor at IIITDM Kancheepuram, where she joined in Dec. 2008. She did her B Tech in electronics and communication engineering from Calicut University, Kerala and both MTech and PhD from the Microelectronics and MEMS Laboratory, Department of Electrical Engineering, IIT Madras. She has published about 12 international journal papers and 24 international conferences. Her areas of interests include MOS and MIS devices and analog VLSI circuits. Corresponding author. Email: [email protected]