Empirical Drain Current Model of Graphene Field-Effect Transistor for Application as a Circuit Simulation Tool

Abstract

In this paper, an empirical model of dual gate graphene field-effect transistor (GFET) has been developed. The explicit form of drain current expression has been established analytically based on a drift-diffusion approach. The channel sheet charge density helps us to determine the quantum capacitance more accurately. The channel potential has been derived from the equivalent circuit. The improvement of carrier mobility has been included. The closed form expression is obtained with a few fitting parameters to explore the model characteristics. The model is also valid for single gate technology. The model has been verified against some pioneering experimental results reported in literatures. Model simulation agrees well with existing experimental data. We have also compared the results of the model obtained from NANOHUB online simulator for further verification. The characteristics of small signal parameters of this GFET model have been observed and cut-off frequency has been determined. The developed analytical GFET model is also found to be computationally efficient. It is observed that with ± 10% variation in top gate oxide thickness, maximum drain current and peak transconductance vary by (−11.53%/ + 14%) and (−25%/+31.25%), respectively. The double gate bilayer GFET model is implemented in Verilog-A and verified for a voltage amplifier in SPICE environment.

KEYWORDS:

• GFET
• model
• MOSFET
• NANOHUB
• Quantum capacitance
• Verilog-A
• SPICE

Additional information

Funding

This work was supported by SMDP-C2SD Project, MeiTY, Government of India.

Notes on contributors

Sudipta Bardhan

Sudipta Bardhan received MTech degree in VLSI design and microelectronics technology from Jadavpur University, Kolkata, India, in 2009. He is currently pursuing PhD degree in the School of VLSI Technology, Indian Institute of Engineering Science and Technology, Shibpur, Howrah, India. His current research interests include the modelling and simulation of nanoscale devices. Email: [email protected]

Manodipan Sahoo

Manodipan Sahoo (M'17) currently is a faculty member of Indian Institute of Technology (Indian School of Mines), Dhanbad, India. His research interests include modeling and simulation of nano-interconnects and nano-devices, VLSI circuits and systems. He has published several articles in archival journals and refereed conference proceedings. Corresponding author. Email: [email protected]

Hafizur Rahaman

Hafizur Rahaman (SM'10) currently is a faculty member of Indian Institute of Engineering Science and Technology (IIEST), Shibpur, India. His research interests include design and testing of Integrated Circuits, nano-biochips and emerging nanotechnologies including reversible quantum computing. He has published more than 300 research articles in archival journals and refereed conference proceedings. Email: [email protected]