Optimization of Dual-K Gate Dielectric and Dual Gate Heterojunction SOI FinFET at 14 nm Gate Length

Abstract

Modification of process parameters of the Fin shaped Field Effect Transistor (FinFET) is the field of research which has drawn attention after it has been inferred that these transistors diminish the leakage effects, which occur in planar transistors. The research paper presents a novel approach in which Artificial Neural Network (ANN) and Genetic Algorithm (GA) have been combined to optimize the structure of 14 nm Dual Gate Material Dual Gate Dielectric Material Heterojunction (DGMDGDM-Hetero) Silicon On Insulator (SOI) FinFET. The dataset mandatory for the training of ANN has been obtained through designing and simulating the DGMDGDM-Hetero SOI FinFET structure by varying the Si_1-xGe_x height (H_SiGe) and mole fraction (MF_SiGe) in TCAD simulator. Through GA optimization, the optimal value of H_SiGe and MF_SiGe for which minimum Subthreshold Swing (SS), off-current (I_d,off), Drain-Induced-Barrier-Lowering (DIBL) along with maximum on-current (I_d,on) and I_d,on–I_d,off ratio achieved have been discovered. The considered FinFET structure was designed and simulated with optimal value of H_SiGe and MF_SiGe which resulted in ultimate best performance parameters. DIBL and leakage of 15.8 mV/V and 1.37 × 10⁻¹⁷A respectively, suggesting that DGMDGDM-Hetero SOI FinFET has more control over undesired Short Channel Effects (SCEs). Only 1.4% difference in the value of ANN-GA optimized and TCAD simulated performance parameters substantiate the effectiveness of optimization process.

Keywords:

• ANN
• Drain-induced barrier lowering
• Dual gate material
• GA
• Heterojunction SOI FinFET
• Leakage current
• Subthreshold swing

Acknowledgement

The resources provided for the research work implementation are highly acknowledged so the authors are highly obliged to Dr M S Saini, Director, Guru Nanak Dev Engineering College, Ludhiana, Punjab.

Additional information

Notes on contributors

Samjot Kaur Aujla

Samjot Kaur Aujla did her BTech in 2015 and currently pursuing MTech in electronics and communication engineering from Guru Nanak Dev Engineering College, Ludhiana. Her areas of interest include internet of things, nanoscale device designing, signal and image processing and nature inspired algorithms. Corresponding author. Email: [email protected]

Navneet Kaur

Navneet Kaur did her MTech in 2011. Currently, she is pursuing PhD and working as assistant professor in department of ECE at Guru Nanak Dev Engineering College, Ludhiana, Punjab. Her research interests include VLSI design, semiconductor devices, signal processing and soft computing techniques. She has published more than 30 papers in international and national journals and conferences of repute. She has authored one book and also contributed one chapter in a book. She is a member of professional society; IEEE communication society. Email: [email protected]