Performance and Power Optimization for Intercalation Doped Multilayer Graphene Nanoribbon Interconnects

Abstract

In this work, thickness of AsF5 intercalation doped, Multilayer Graphene Nanoribbon (MLGNR) interconnects is optimized by minimizing various performance and power metrics (i.e. crosstalk-induced signal transmission delay, noise parameters, Noise-delay product (NDP), Energy-delay product (EDP), Power-delay product (PDP) and Noise bandwidth ratio (NBWR)). For perfectly and nearly specular MLGNRs (i.e. specularity index, P = 1 and P = 0.8 respectively), the optimal thicknesses for minimizing the crosstalk-induced delay are 25 nm and 100 nm for intermediate and global level MLGNR interconnects, respectively. However, it is observed that perfectly and nearly specular MLGNRs are immune to noise for thickness less than 40 nm at intermediate level and 200 nm at global level interconnects. They outperform Cu in terms of signal transmission delay, noise width and noise area at both levels of interconnect. But in terms of peak crosstalk noise, Cu is better than all types of MLGNR interconnects. When we talk about NDP, EDP and NBWR, MLGNR thickness optimizes at 25 nm for intermediate level and 100 nm for global level. As far as power dissipation is concerned, perfectly and nearly specular, intermediate and global level MLGNRs are many times better than copper in the whole range of its thickness which can be optimized by minimizing its PDP at 100 nm irrespective of the level of interconnects. It can be inferred from the simulated results that global level MLGNR interconnects are amenable to scaling, whereas intermediate level interconnects have adverse effects of scaling.

KEYWORDS:

• Crosstalk
• Delay
• EDP
• MLGNR interconnects
• Noise
• NDP
• NBWR
• Optimization
• PDP

Notes

1 A Preliminary version of this work has appeared in ref. [21].

Additional information

Funding

This work was partially supported by TEQIP III [TEQIP/PRJ/006/18-19] under National Project Implementation Unit, Ministry of Human Resource Development (MHRD) funded at IIT (ISM), Dhanbad.

Notes on contributors

Bhawana Kumari

Bhawana Kumari received MTech degree in VLSI design from ABV-IIITM, Gwalior, India, in 2017. She is currently pursuing PhD degree in the department of Electronics Engineering, Indian Institute of Technology (Indian School of Mines), Dhanbad, India. Her current research interests include the modeling and simulation of nano-interconnects.

Manodipan Sahoo

Manodipan Sahoo currently is a faculty member of Indian Institute of Technology (Indian School of Mines), Dhanbad, India. His research interests include modeling and simulation of nano-interconnects and nano-devices, VLSI circuit and systems. He has published articles in archival journals and refereed conference proceedings. Email: [email protected].