Oversampled CI-OFDM Baseband Transceiver Architecture and Its FPGA Prototype

Abstract

Orthogonal frequency division multiplexing (OFDM) scheme has been widely employed in the wireless communication systems. However, the scheme suffers a limitation of high peak to average power ratio (PAPR). Carrier Interferometry (CI) codes proved to be an efficient PAPR reduction method but these CI codes when employed with OFDM (CI-OFDM), acts as a single-carrier modulation scheme. To retain the principle of multi-carrier modulation and gain the advantage of low PAPR using CI codes, a new efficient oversampled CI-OFDM scheme is proposed in this paper. Furthermore, the architecture for the oversampled CI-OFDM transceiver with two modulation schemes is proposed and prototyped on the commercially available virtex5 FPGA device in the laboratory experimental setup. The proposed scheme exhibits a PAPR reduction of minimum 4 dB, and a bit error rate (BER) of ${10}^{-4}$ is achieved for a signal to noise ratio (SNR) of 8.4 dB. To analyse the behaviour of the proposed scheme, various hardware performance parameters in terms of occupied bandwidth, channel power of main lobes and side lobes are measured, and the total bandwidth is found to be 240 KHz. The hardware resource utilization of the proposed architecture is also reported.

Keywords:

• CI-OFDM
• Cyclic prefix
• Fixed point AWGN channel
• FPGA prototype
• OFDM
• Oversampling
• PAPR

Acknowledgments

The authors would like to thank MeitY, Govt. of India, for funding of this research under the project entitled “Design and FPGA Prototype of Multicarrier Multiple Access Schemes for Variable Rate Multimedia Satellite Communication”, Project Reference No. R&D/SP/EE/DEIT/DFP/2013-14/61.

Additional information

Notes on contributors

Rakesh Palisetty

Rakesh Palisetty is currently a PhD research scholar in Electrical Engineering Department, Indian Institute of Technology – Patna, India. He received his MTech degree in VLSI design from GITAM University in 2013 and BTech degree in electronics and communication engineering from SISTAM College of Engineering in 2011. His research interests include VLSI for communication, VLSI architectural design and FPGA-based system design.

Kailash Chandra Ray

Kailash Chandra Ray received the BE degree in electrical engineering from the Orissa Engineering College, Bhubaneswar, India, in 1997, the MTech degree in electrical engineering from NIT, Jamshedpur, India, in 2000, and the PhD degree in electronics and electrical communication engineering from IIT Kharagpur, India, in 2009. He was a Technical Member Staff (Design Engineer) with CMOS Chips, Bangalore, India, during 2001–2003. He also served as a lecturer with IIIT Allahabad, India, from 2008 to 2010. He was an assistant professor with the Department of Electrical Engineering, IIT Patna, India, from 2010 to 2018, where he has been an associate professor since 2018. His research interests include very large-scale integration (VLSI) architectural design, VLSI signal processing, digital VLSI design, hardware design methodologies, FPGA-based system design, CORDIC, and embedded system. Email: [email protected]