A Novel Slice-Based High-Performance ALU Design Using Prospective Single Electron Transistor

Abstract

The arithmetic logic unit (ALU) is one of the most essential components of any microprocessor or computing system that is capable of performing several arithmetic as well as logic operations. For realizing efficient and high-performance ALU, proper designing, optimum selection of materials and incorporation of advanced devices are utmost important. The single electron transistor (SET) is a prominent advanced device structure for achieving high-end computing system. In this paper, the prospective SET-based ALU is realized to meet next-generation requirements like higher speed, lower power, and volume. Also, the enhancement capability of ALU can be further accomplished by incorporating effective modular design using slice-based approach. The slice-based design approach provides simplicity and extensibility of the design. In this, each slice has the capability to perform arithmetic and logical operations on one-bit input data. Henceforth, cascading of n such slices generates the n-bit ALU. The multiplication operation is executed separately. The incorporation of separate multiplier block aids in achieving fast execution of multiplication operation with a single instruction. The performance of high-end proposed SET-based ALU is compared with the conventional complementary metal oxide semiconductor (CMOS) and 18 nm FinFET technology-based ALU designs. It is observed that the SET-based ALU gives 1.9× lesser delay and 19.8× lower power dissipation as compared to its 16 nm CMOS counterpart. Also, with respect to 18 nm FinFET-based technology, proposed SET-based design out-stands extensively in terms of lower transistor count and power.

Keywords:

• Arithmetic logic unit
• Combinational circuits
• Logic design
• Multiplier
• Single electron transistor
• Slice approach

Disclosure statement

No potential conflict of interest was reported by the authors.

Additional information

Notes on contributors

Rashmit Patel

Rashmit Patel received the BE degree in electronics and communications from North Gujarat University, Gujarat, India, in 1997. He is working with Space Applications Centre, Indian Space Research Organization (ISRO) since 1998. His research interests include design and developments of space qualified hardware, integrated system, telemetry processor, MIL-STD-1553 controller, FPGA-based circuits, computer designs and SET-based complex system simulation. He has designed, developed, characterized and delivered various camera electronics circuit blocks for payloads of ISRO space programs. At present he is pursuing PhD with Dhirubhai Ambani Institute of Information and Communication Technology.

Yash Agrawal

Yash Agrawal received the BE degree in E&CE from KITS, Ramtek, Maharashtra, India, in 2009 and MTech and PhD degrees in VLSI design automation and techniques from National Institute of Technology, Hamirpur, Himachal Pradesh, India, in 2012 and 2016, respectively. Presently, he is working as Faculty at DA-IICT Gandhinagar, Gujarat. His current research interests include nanotechnology, modeling and analysis of nano devices and interconnects. He was a university rank holder during his Bachelor's degree. He achieved third place in All India Mentor Graphics design contest held at Bangalore, India, in 2011. He has been the chairman and awarded with best forum member of IETE Forum at KITS Ramtek, Nagpur Division during 2008–2009. He has also been awarded first rank in various national and inter-college level paper presentations. He is a member of IEEE. Email: [email protected]

Rutu Parekh

Rutu Parekh did her MEng in electrical engineering from Concordia University, Montreal, Canada, PhD in electrical engineering (nanoelectronics) from Université de Sherbrooke, Sherbrooke, Canada and as a postdoctoral fellow at Centre of Excellence in Nanoelectronics, IIT Bombay in 2015. Her research interest includes developing of models, co-design methodology and co-simulation of hybrid circuits of emerging nanoelectronic devices with CMOS technology, developing ASIC for astronomy instrumentation, low voltage and low power circuits, phase change memory, MEMS devices, embedded systems and IOE. She has research experience with École Polytechnique de Montréal, industrial experience with eInfochips, Ahmedabad, India and HP Karkland, Montreal, and teaching experience with Nirma University of Science and Technology, Ahmedabad. She is currently working as an assistant professor at DA-IICT, Gandhinagar, India. She is also associated with The Inter-University Centre for Astronomy and Astrophysics, Pune, India, as a Visiting Associate.Email: [email protected]