CMOS Analog Amplifier Circuits Design Using Seeker Optimization Algorithm

Abstract

This article proposes an area optimized design approach for two different analogue VLSI circuits: current mirror load based CMOS differential amplifier circuit and CMOS two-stage operational amplifier. The evolutionary method utilized for these optimal designs is the Seeker Optimization Algorithm (SOA). Human searching capability and understanding are modelled in SOA. In SOA, the search direction is based on the empirical gradient, and the step length is based on some simple fuzzy rule. In this article, SOA is employed to optimize the sizes of the MOS transistors to reduce the overall MOS area occupied by the circuit while satisfying the design constraints. The results obtained from the SOA technique are validated in SPICE environment. SPICE-based simulation results justify that SOA is a much better technique in comparison with the other formerly reported methods for the designs of the circuits mentioned above in terms of MOS area, gain, power dissipation, etc.

KEYWORDS:

• Differential amplifier
• Low power design
• Optimization
• SOA
• Transistor sizing
• Two-stage Op-amp

Additional information

Notes on contributors

K. B. Maji

Kanchan Baran Maji passed BTech degree in electronics and communication engineering from Haldia Institute of Technology, West Bengal, India in the year 2006. He received MTech degree in microelectronics and VLSI from NIT, Durgapur, West Bengal, India in the year 2015. He is pursuing PhD from National Institute of Technology, Durgapur, West Bengal, India. His research interest includes VLSI circuit optimization via evolutionary optimization techniques. Corresponding author. Email: [email protected]

B. P. De

Bishnu Prasad De passed BTech degree in electronics and communication engineering from Jalpaiguri Government Engineering College, West Bengal, India in the year 2007. He received MTech degree in VLSI design from IIEST, Shibpur, West Bengal, India in the year 2009. He received the PhD degree from National Institute of Technology, Durgapur, West Bengal, India in the year 2016. He worked as an assistant professor at Haldia Institute of Technology, West Bengal, India for more than seven years. In 2017, he joined at KIIT deemed to be University, Bhubaneswar, Odisha, India and currently, serves as an assistant professor (II). His research interests include nano-scale device modelling and characterization, analog and mixed signal IC design, RF integrated circuit design. Email: [email protected]

R. Kar

Rajib Kar passed BE degree in electronics and communication engineering, from Regional Engineering College, Durgapur, West Bengal, India in the year 2001. He received the MTech and PhD degrees from National Institute of Technology, Durgapur, West Bengal, India in the year 2008 and 2011, respectively. Presently, he is attached with National Institute of Technology, Durgapur, West Bengal, India, as an associate professor in the Department of Electronics and Communication Engineering. His research interest includes VLSI circuit optimization, signal processing via evolutionary computing techniques. He has published more than 350 research papers in international journals and conferences. Email: [email protected]

D. Mandal

Durbadal Mandal passed BE degree in electronics and communication engineering from Regional Engineering College, Durgapur, West Bengal, India in the year 1996. He received the MTech and PhD degrees from National Institute of Technology, Durgapur, West Bengal, India in the year 2008 and 2011, respectively. Presently, he is attached with National Institute of Technology, Durgapur, West Bengal, India, as an associate professor in the Department of Electronics and Communication Engineering. His research interest includes array antenna design; filter optimization via evolutionary computing techniques. He has published more than 300 research papers in international journals and conferences. Email: [email protected]

S. P. Ghoshal

Sakti Prasad Ghoshal passed BSc and BTech, degrees in 1973 and 1977, respectively, from Calcutta University, West Bengal, India. He received MTech degree from IIT (Kharagpur) in 1979. He received PhD degree from Jadavpur University, Kolkata, West Bengal, India in 1992. Presently, he is acting as professor of Electrical Engineering Department of NIT Durgapur, West Bengal, India. His research interest areas are application of evolutionary computing techniques to electrical power systems, digital signal processing, array antenna optimization and VLSI. He has published more than 300 research papers in international journals and conferences. Email: [email protected]