A High-Speed, Low-Power, and Area-Efficient FGMOS-Based Full Adder

Abstract

Full adder is one of the fundamental components of very large-scale digital integrated systems, capable of performing all arithmetic operations. High-performance full adders are always desired to meet the challenges of ever growing integration technology. This paper presents the design of a full adder using floating-gate MOSFET (FGMOS). FGMOS is a multi-input transistor where the input signals are capacitively coupled to the floating gate, and the effective threshold voltage can be lowered from its conventional value. The voltage on the floating-gate is the weighted sum of the input voltages applied at the multiple input gates. This feature of FGMOS has been exploited in this paper for designing a high-speed, low-power, and area-efficient full adder. The performance of FGMOS-based full adder has been compared with other full adder designs available in the literature. It has been observed that FGMOS-based full adder exhibits better performance in terms of propagation delay, power consumption, and power delay product besides consuming less chip area due to the reduced transistor count compared with existing full adder designs. The workability of these circuits has been verified by PSpice simulations carried out using level 7 parameters in 0.13 µm CMOS technology with supply voltage of 1 V. The simulation results have been found to be in good conformity with the mathematical formulations.

KEYWORDS:

• CMOS
• CPL
• Delay
• FGMOS
• Full adder
• GDI

Additional information

Notes on contributors

Roshani Gupta

Roshani Gupta received her MSc and MPhil degrees in electronics in the years 2011 and 2014, respectively. She received her PhD degree in electronics in 2018 from the University of Jammu. She has 24 publications in national/international conferences and journals. Email: [email protected]

Rockey Gupta

Rockey Gupta received his MSc degree in electronics from University of Jammu in 2000 with gold medal. He received his PhD degree in electronics in 2014 from the same university. Presently, he is working as a senior assistant professor in Department of Electronics, University of Jammu. He has 30 publications to his credit in various national/international conferences and journals. He is a life member of Institution of Electronics and Telecommunication Engineers (IETE), India, and Indian Science Congress. Corresponding Author. Email: [email protected]

Susheel Sharma

Susheel Sharma received his MSc physics (Electronics) from University of Jammu in 1991 and PhD degree from the same University in 2007. Presently, he is professor in Department of Electronics, University of Jammu, and his area of research interest includes low voltage analog and digital integrated circuits. He has 44 publications to his credit in various national/international conferences and journals. He is a life member of Institution of Electronics and Telecommunication Engineers (IETE), India, and Indian Science Congress. Email: [email protected]