Performance Analysis of Multipliers Using Modified Gate Diffused Input Technology

Abstract

The primitive constraints in any VLSI system design are power, delay and area. Systems based on CMOS logic consume more power and area. Higher power dissipation will have a direct effect on the lifetime and performance of digital systems. Adders and multipliers form the core of almost all the digital systems like Microprocessor, Digital Signal Processors (DSPs), etc., so the adders and multipliers need to be optimized in terms of power, area and delay for an efficient and cost-effective processor design. This paper presents an approach for implementing 8-bit Array multiplier, Wallace Tree multiplier and Vedic multiplier using modified Gate Diffusion Input (m-GDI) technology and comparative analysis against area, power and delay. From the analysis, it is found that multipliers, which are built on m-GDI logic, occupy less area, dissipate less power and experience less delay than the multipliers based on CMOS logic, GDI logic and Booth multiplier. Also among the three m-GDI-based multipliers, Vedic multiplier performs better in terms of area, speed and power than array multiplier and Wallace tree multiplier.

KEYWORDS:

• Array multiplier
• Digital signal processor
• Modified gate Diffusion input (m-GDI)
• Power dissipation
• Vedic multiplier
• Wallace Tree multiplier

Additional information

Notes on contributors

Y. G. Praveen Kumar

Y G Praveen Kumar obtained his BE degree in electronics and communication engineering from VTU, Belagavi, Karnataka, India in 2008 and master of technology in VLSI design and embedded systems from the same University in 2010. He has been working as assistant professor in the Department of Electronics and Communication Engineering, Sri Siddhartha Institute of Technology, Tumakuru, Karnataka, India for 9 years. He is a life member in Indian Society for Technical Education (ISTE). He has authored/co-authored more than 25 articles in refereed international journals and conferences. His research interests are in the areas of VLSI system design, low power applications, digital design. Corresponding author. Email: [email protected]

B. S. Kariyappa

B S Kariyappa obtained his BE degree in electronics and communication from Bangalore University, in 1997, ME degree in electronics and communication from the same University in 2000, and the PhD degree in electronics and communication from Avinashlingam University for Women, Coimbatore in 2012. He is currently working as a professor in the Department of Electronics and Communication Engineering, R V College of Engineering, Bengaluru. With over 18 years of teaching experience, he is guiding 4 PhD students and guided many undergraduate and postgraduate projects. He has authored/co-authored more than 25 articles in refereed international journals and conferences. He is a life member in Indian Society for Technical Education (ISTE) and Institution of Electronics and Telecommunication Engineers (IETE). His research interests include the areas of VLSI design, microprocessor and microcontroller-based system designs, embedded system design. Email: [email protected]

S. M. Shashank

Shashank S Meti obtained his BE degree in electronics and communication engineering from Basaveshwar Engineering College, Bagalkot in 2015. He is currently pursuing MTech degree in VLSI design and embedded systems at R V College of Engineering, Bengaluru. His research interests include the areas of VLSI design, analog design and digital system design. Email: [email protected]

C. N. Bharath

C N Bharat obtained his BE degree in electronics and communication engineering from Sir M V Institute of Technology, Bengaluru in 2015. He is currently pursuing MTech degree in VLSI design and embedded systems at R V College of Engineering, Bengaluru. His research interests include the areas of VLSI design, analog design and digital system design. Email: [email protected]