Design and Simulation of Reliable Low Power CMOS Logic Gates

Abstract

In this paper, a circuit-level reliable low leakage design methodology is proposed for integrated circuits (ICs). Low leakage circuit design is the most challenging research area for very large-scale integration (VLSI) circuit designers due to the increased demand of battery-operated portable systems. Leakage power is increasing continuously with each new technology node generation in deep sub-micron (DSM) regime. Large power dissipation harms the device characteristics and affects the overall performance of the circuits. Proposed approach is extensively discussed and verified for the low power operation and reliability. The various logic circuits are simulated and compared with the available leakage minimization techniques at 22 nm technology node using predictive technology model (PTM) bulk CMOS BSIM4 on HSPICE tool. Proposed approach reduces leakage power by ≈81% in XOR2 and XNOR2 gates as compared to conventional CMOS gates. Reliability of the nanoscaled circuits is affected by several device parameters. Process, voltage and temperature (PVT) variations, aging and radiation effects are considered for reliability testing. The reliability of the proposed approach is improved by 77.45% for power delay product (PDP) metric for the ring oscillator as compared to conventional circuit.

KEYWORDS:

• Device scaling
• DSM regime
• Low power VLSI
• Monte-Carlo simulation
• Nanoscaled CMOS
• Stacking

Additional information

Notes on contributors

Vijay Kumar Sharma

Vijay Kumar Sharma received his BTech degree in electronics and communication engineering from UPTU, Lucknow, India, in 2007 and MTech in VLSI design from National Institute of Technology, Hamirpur, India, in 2009. He obtained his Ph.D. degree in low power VLSI design in the Department of Information Technology at the ABV Indian Institute of Information Technology and Management, Gwalior, India. He has published more than 35 research articles in various reputed international/national journals/conferences. He is the author of two books on low power CMOS circuits. His research interest includes low power, high performance and variability aware nanoscale CMOS circuit design.