Investigation of Homo and Hetero-Junction Double-Gate Tunnel-FET-Based Adiabatic Inverter Circuits

Abstract

This paper compares the performance of adiabatic inverter circuits employing homo/hetero-junction-based double-gate tunnel field-effect transistors (DG-TFETs). The static and dynamic adiabatic inverter circuits are constructed and they are operated by a sinusoidal power clock signal. The static adiabatic inverter circuits quasi-static energy recovery logic (QSERL), complimentary energy path recovery logic (CEPAL), glitch-free cascadable adiabatic logic (GFCAL) and dynamic adiabatic inverter circuits, clocked adiabatic logic (CAL), pass-transistor adiabatic logic (PAL), single-phase source coupled adiabatic logic (SCAL) are taken into consideration. The circuit performances are evaluated in terms of their power dissipation and delay. In static adiabatic inverter circuits, the homo/hetero-TFET-based GFCAL circuit shows better performance in terms of power and delay than QSERL and CEPAL. In dynamic adiabatic inverter circuits, the homo/hetero-TFET-based PAL circuit demonstrates better improvement in terms of power and delay than CAL and SCAL.

KEYWORDS:

• CAL
• CEPAL
• Delay
• DG-TFETs
• Energy recovery logic
• GFCAL
• PAL
• Power dissipation
• QSERL

Acknowledgements

This work is supported by the Department of Science and Technology, Government of India under SERB scheme (grant number SERB/F/2660).

Additional information

Funding

This work is supported by the Department of Science and Technology, Government of India under SERB scheme [grant number SERB/F/2660].

Notes on contributors

M. Pown

M Pown is pursuing her doctoral degree in electronics and communication engineering in Vellore Institute of Technology, Chennai, India. She received her BE (Electronics and Communication Engineering) and ME (VLSI Design) degrees from Anna University, Chennai, India, in 2012 and 2014, respectively. From 2014 to 2017, she was a research fellow of the DST-SERB at VIT, Chennai. Her research interests include semiconductor device design, mixed signal integrated circuit design and simulation. Email: [email protected]

S. Sandeep

S Sandeep obtained his ME in mechatronics and artificial intelligence from Victoria University of Wellington, New Zealand in 2019 and MTech degree in VLSI design from Vellore Institute of Technology, Chennai, India in 2017. He received his BTech degree in electrical and electronics engineering from the University of Kerala, India in 2014. Currently, he is working as a robotics engineer in Greentech Robotics, New Zealand. His research areas are VLSI, adiabatic logic, mechatronics, robotics and computer vision. Email: [email protected]

B. Lakshmi

B Lakshmi obtained her doctoral degree in information and communication engineering from Anna University, Chennai, in 2013. She received her ME (Applied Electronics) from Anna University, Chennai, in 2005 and BE (ECE) from Madras University in 2000. She is currently working as a professor in the School of Electronics Engineering, VIT, Chennai. Her research interests include VLSI, nano-scale transistors, and micro/nanoelectronics. She successfully completed a project for DST- SERB titled, “Process variational study and performance analysis of nano-scale MOSFETs and Tunnel FETs: Tunnel FETs based mixed signal integrated circuits for system-on-chip applications” in 2017. To her credit, she has 25 journal papers and 10 conference papers.