A Fault-Tolerance Nanoscale Design for Binary-to-Gray Converter based on QCA

ABSTRACT

The very-large-scale-integration industry has been highly trying to attain miniaturization. This function causes several challenges regarding size, switching speed, power, and fault-tolerant at the nanoscale. Quantum-dot cellular automata (QCA) can contain a remarkable reduction in scale, fast switching rate, ultra-low energy consumption, and high fault-tolerant. Thus, fault-tolerant logic has attained the attention of several investigators in the QCA science domain. On the other hand, a binary-to-gray converter converts the input data to the gray number to facilitate error correction in digital communication. So, in the present investigation, we have demonstrated a structure of fault-tolerant binary-to-gray converter in QCA employing the majority gate, inverter gate, and cell redundancy on the wire. With the utilization of the QCADesigner 2.0.3 simulator, we have simulated and tested proposed circuits. In this paper, four factors, namely single-cell missing, displacement, misalignment, and extra single-cell, have been inspected by simulation software. The proposed fault-tolerant two-bit, three-bit, and four-bit binary-to-gray converter could attain 100% fault tolerance while a single missing defect existed in the layout.

KEYWORDS:

• Converter
• Quantum-dot cellular automata
• Gray
• Fault-tolerant
• Cost
• Binary

Additional information

Funding

This work was supported in part by the Ministry of Science and Technology (MOST), Taiwan, under Grant MOST 110-2222-E-224-002-MY3.

Notes on contributors

Saeid Seyedi

Saeid Seyedi is a researcher at the Young Researchers and Elite Club, IAU since 2018. His current research is concerned with QCA-based technology and nano, and he has worked on many research projects. He has published papers in various journals and conference proceedings. His research interests include nanotechnology, quantum-dot cellular automata, VLSI, fault-tolerance hardware, and cloud computing. Email: [email protected]

Nima Jafari Navimipour

Nima Jafari Navimipour received his BSc, MSc, and PhD degrees in computer engineering from Islamic Azad University, Iran, in 2008, 2009, and 2014, respectively. Dr Navimipour also is a technical committee member, guest editor, and associate editor of some high-ranked journals such as IET Quantum Communication, Computer Communication, Cluster Computing, and Kybernetes. Furthermore, he is a chair member of many prestigious conferences and a reviewer of several high-ranked journals. He has been giving invited tutorials/talks in IEEE conferences and has been invited to give lectures in different universities. Nima also won the Publons Top Peer Review Awards in 2018 and 2019. Dr Navimipour has been featured among the World's Top 2% Scientists List, according to a conducted study by US-based Stanford University in 2020. His research interests include cloud and distributed computing, Internet of Things (IoT), Software-Defined Networking (SDN), computational intelligence, evolutionary computing, and quantum computing. He has published many papers in various journals and conference proceedings as well as supervising/co-supervising several PhD and Master's students in these research areas.