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Abstract
A hardware-based memory-efficient sequence alignment architecture is described in this paper. This paper expresses a comprehensive blueprint of the hardware implementation of compact sequence alignment for pair-wise global alignment technique to achieve high-throughput processing. This architecture uses SRAM and only a small amount of digital logic circuitry to perform elementary operations of sequence alignment in real time. Additionally, this alignment engine does not require any preprocessing operations like in most of the existing alignment approaches do. Furthermore, it does not call for any sort of comparison mechanism for preparing final sequence alignment by the alignment co-processor. The entire architecture is simulated and synthesized in FPGA board for numerous cases considering dissimilar pseudo-randomly generated sequence pairs with variable sequence lengths ranging from 16 to 2048 nucleotides. The proposed design exhibits compact alignment of the sequences that leads to the identification of close similarity between the sequences under test. Moreover, the proposed alignment engine takes significantly less amount of time, ≈64–95% less time, and ≈85–99% less amount of memory space than existing alignment approaches. The overall system performance is studied with respect to Millions Alignments Per Second (MAPS) and exhibits ≈55–75% more sequence alignments of same set of DNA sequences in a stipulated time compared to existing schemes.
Acknowledgments
This work is supported and funded under grant no. BT/PR16378/BID/7/600/2016 by the Department of Biotechnology, Ministry of Sc. and Tech., Govt. of India.
Additional information
Funding
Notes on contributors
Ardhendu Sarkar
Ardhendu Sarkar received BTech degree in computer science & engineering from GCETTB, India, in 2012, and MTech in information technology from IIEST Shibpur, India in 2016 He served as JRF for DBT, MST, Govt. of India sponsored project and currently working as JRF (PhD Scholar) attached to the Department of Computer Science and Technology of IIEST, Shibpur, Howrah, WB, India. His current research interests are in computer architecture, embedded systems and image processing. E-mail: [email protected]
Surajeet Ghosh
Surajeet Ghosh received BTech (CST), ME (CSE) and PhD (Engg) degrees from Kalyani University – Kalyani, West Bengal University of Technology – Kolkata and Jadavpur University – Kolkata in 2002, 2005 and 2017, respectively. He has more than 14 years of teaching and research experience. He received IETE-Gowri Memorial Award 2008 and Best Paper Award at IEEE International Conference on Computational Intelligence and Computing Research (IEEE ICCIC) 2013. He acted as a Session Chairman in various conferences like IEEE ISVLSI 2019, IEEE ANTS 2015, IEEE TENCON 2017, etc.He is a Life Member of IETE, Member of IEEE and IEEE Computer Society. His current research interests are in in computational architecture for next generation sequencing, internet of things, and FPGA based embedded system design.
Sanchita Saha Ray
Sanchita Saha Ray currently working as assistant professor in St Thomas College of Engineering and Technology, Kolkata. She received her BTech in ECE from the Sikkim Manipal Institute of Technology and ME in CSE from West Bengal University of Technology. She received Bronze Medal in ME (CSE). She received the IETE-Gowri Memorial Award 2008 and best paper Award in IEEE ICCIC 2013. Her research includes network packet processing, HPC for biological sequences and high performance computer architecture. She has published more than 15 international journal and conference papers. She reviewed manuscripts in IEEE TVLSI and IEEE Communications Letters. E-mail: [email protected]