DTMOS Based Low Power Adaptively Biased Fully Differential Transconductance Amplifier with Enhanced Slew-Rate and its Filter Application

ABSTRACT

An efficient implementation of low-voltage low power two stage fully differential transconductance amplifier using CMOS technology is proposed. In this work, the dynamic threshold voltage MOSFET (DTMOS) and unique adaptive biasing technique are used to obtain the enhanced slew-rate with minimized power supply overhead. This dynamic threshold MOS based fully differential OTA operates at ±0.5 V dual supply voltage. It provides average slew-rate as168 V/μS with 0.104 mW static power consumption. The dc gain of the circuit is calculated as 73.86 dB with a 72° phase margin. The figure of merit of proposed OTA is 16.15 [(V/µs).pF/µW] for the load capacitor of 10 pF, which shows significant improvement compared to prior work. To validate the robustness of the proposed design universal voltage mode filter is designed and simulated as its application. Mentor Graphics Eldospice with 0.18 μm TSMC level 53 CMOS technology has been used to verify the performance of the proposed circuit and its application.

KEYWORDS:

• Active filter
• Adaptive biasing
• Dynamic threshold voltage MOSFET (DTMOS)
• Figure of merit
• Fully differential operational transconductance amplifier (OTA)
• Slew rate

Correction Statement

This article has been corrected with minor changes. These changes do not impact the academic content of the article.

Additional information

Notes on contributors

Mihika Mahendra

Mihika Mahendra received the BE degree from Rashtrasant Tukadoji Maharaj Nagpur University, India. She received the M.Tech degree from Yeshwantrao Chavan College of Engineering, Nagpur, India. She has been working as assistant professor in Electronics and Communication Department of Tulsiramji Gaikwad-Patil College of Engineering and Technology, Nagpur, India, since year 2013. She is currently working as a research scholar in Faculty of Technology, University of Delhi, New Delhi, India. Her research focuses on the design of low power analog integrated circuits. Email: [email protected]

Shweta Kumari

Shweta Kumari received BTech degree in electronics and communication engineering from UP Technical University, Lucknow and MTech degree in integrated electronics and circuits from Indian Institute of Technology Delhi, India in 2004 and 2010, respectively. During 2004-2005, she was a lecturer in VIET, Dadri, India. During 2005–2008, she was a lecturer in Inderprastha Engineering College, Ghaziabad, India. She again joined the same College as assistant professor, from 2011–2014. She is currently working towards the PhD degree at Netaji Subhas Institute of Technology (NSIT), New Delhi, India. Since October 2014, she has been with NSIT, where her research focuses on the design of analog integrated circuits. She has thorough experience in working with various industry-standard VLSI design tools (Tanner EDA, Mentor Graphic tool, Cadence Virtuoso). Email: [email protected]

Maneesha Gupta

Maneesha Gupta is the corresponding author for this manuscript. She received BE and ME, in electronics and communication engineering from Government Engineering College, Jabalpur, India, and her PhD from the Department of Electronics Engineering, Indian Institute of Technology, New Delhi, India. She is currently working as a professor in the Department of Electronics and Communication Engineering, Netaji Subhas University of Technology (formerly known as Netaji Subhas Institute of Technology), New Delhi, India. Her teaching and research interests are switched capacitors circuits, analog and digital signal processing, low voltage low power design techniques, and fractional-order analog and digital circuits. She is author and co-author over 100 research papers in these areas in various international/national journals and conferences. She got the best paper award for her paper in the IETE Journal of Education in 2001. Corresponding author. Email: [email protected]