An Efficient Obstacle-Avoiding Rectilinear Steiner Tree Construction Method Using PB-SAT

ABSTRACT

Rectilinear Steiner tree (RST) construction is an important part of recent VLSI physical design. This article presents an efficient satisfiability (SAT) based approach to construct an obstacle-avoiding Rectilinear Steiner tree for a given set of pins in the presence of a given set of rectilinear obstacles. Initially, a spanning tree is generated without considering the obstacles and the net is decomposed into 2-pin sub-nets. Then, the RST is constructed for each subnet considering obstacles. RST is generated by applying a Pseudo-Boolean (PB) SAT-based technique. The proposed technique has been verified on several benchmark circuits. The results indicate that the proposed technique is able to produce a shorter wire length than other state-of-the-art RST tools in many cases.

Keywords:

• Physical design
• Rectilinear Steiner tree
• Global routing
• Obstacle
• Pseudo-Boolean satisfiability
• Pseudo-Boolean constraints

Disclosure statement

No potential conflict of interest was reported by the author(s).

Additional information

Notes on contributors

Sudeshna Kundu

Sudeshna Kundu received BTech degree in information technology from West Bengal University of Technology, Kolkata, West Bengal, in 2012, and MTech degree in computer science and engineering from the National Institute of Technology Durgapur, West Bengal, in 2014. She is currently pursuing PhD from NIT Durgapur in the Department of Computer Science and Engineering. She also holds the position of assistant professor in University of Engineering and Management, Kolkata in the Department of Computer Science and Engineering. Her current research work includes various satisfiability based approach for solving global routing problems in VLSI physical design.

Suchismita Roy

Suchismita Roy received the BTech degree from the National Institute of Technology, Rourkela, India, the MTech degree from the Indian Institute of Technology Bombay, Mumbai, India, and the PhD degree from the Indian Institute of Technology Kharagpur, Kharagpur, India, all in computer science and engineering. She is currently a professor of computer science and engineering with the National Institute of Technology, Durgapur, India, where she has been a member of the faculty since 1998. Her current research interests include algorithms for very large-scale integration design and test, satisfiability checking, and algorithm design. Email: [email protected]

Shyamapada Mukherjee

Shyamapada Mukherjee received the BE degree in computer science and engineering from the University of Burdwan, India, in 2004, and the MTech degree in computer science and engineering from the University of Calcutta, Kolkata, India, in 2006. He obtained his PhD from NIT Durgapur, India in 2015. Presently, he is an assistant professor at National Institute of Technology Silchar, India. His research interests include algorithms for VLSI design, 3D ICs, satisfiability checking, algorithm design, etc. Email: [email protected]