Dependence of Lateral Straggle Parameter on DC, RF/Analog, and Linearity Performance in SOI FinFET

Abstract

FinFET provide themselves as a strong candidate for low-power applications. However, the enactment of a device depends upon the precision of fabrication process. The ion implantation technique of source/drain region extends towards the channel region and affects the device performance. In this paper, the DC and short channel performances like transfer characteristic, output characteristic, Subthreshold Swing (SS), threshold voltage (V_T), and current ratio (I_on/I_off) of SOI FinFET are reported for the variation in lateral straggle parameter (σ) from 0 to 5 nm. The effect of lateral straggle on various RF/analog figure of merits (FOMs) like transconductance (g_m), output conductance (g_d), intrinsic gain (g_m/g_d), gate capacitance (C_gg), cut off frequency (f_c), and gain frequency product (GFP) are presented for SOI FinFET. Furthermore, the linearity performance such as higher-order harmonics (g_m2, g_m3), voltage intercept point (VIP2, VIP3), input intercept point (IIP₃), intermodulation distortion (IMD₃), and 1-dB compression point are investigated by varying the lateral straggle from 0 to 5 nm. Results reveal that ION = 0.526 mA, g_m  =  0.507 mS, and f_c = 3 THz are obtained at σ  =  5 nm, whereas, VIP2  =  27.5 V and VIP3  =  20.2 V are observed at σ  =  0 nm.

KEYWORDS:

• DC Performance
• FinFET
• Lateral Straggle
• Linearity
• RF/Analog

Disclosure statement

The authors declare that there is no conflict of interest.

Additional information

Notes on contributors

Rajesh Saha

Rajesh Saha is an assistant professor in the Department of Electronics and Communication Engineering Department, MNIT Jaipur, Rajasthan, India. He received PhD from the Department of Electronics and Communication Engineering, National Institute of Technology Silchar, Assam, India, in 2018. He completed his MTech in mobile communication and computing from National Institute of Technology Arunachal Pradesh, Nirjuli, India, in 2015 and BE in electronics and telecommunication engineering from Assam Engineering College, Guwahati, India, in 2012. His research interests include FinFET, Tunnel FET, Ferro-FinFET.

Brinda Bhowmick

Brinda Bhowmick is an associate professor in Electronics and Communication Engineering Department of NIT Silchar, India. She has 80 international journals and 25 international conference articles to her credit. Her research interests include various semiconductor devices like TFET, FinFET, Graphene FETs and device modeling. She received PhD degree from the National Institute of Technology Silchar, Silchar, India, in 2014. She received Visvesvaraya Young Faculty Research Fellowship in 2018.Email: [email protected]

Srimanta Baishya

Srimanta Baishya received the MTech degree in electrical engineering from IIT Kanpur, Kanpur, India, in 1994, and PhD in engineering from Jadavpur University, Kolkata, India, in 2007. He is currently a professor with the Department of Electronics and Communication Engineering, National Institute of Technology Silchar, Silchar, India.Email: [email protected]