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Abstract
Hardware In-Loop Simulation (HILS) test setup is a highly essential tool in the design and development of Aerospace vehicle subsystems. The performance evaluation of vehicle subsystems in real-time scenario helps a lot in achieving successful flight tests and minimizing the number of trials. The HILS testbed suffering from inherent delay during testing and resulted in unwanted diverging oscillations, which limits the HILS testbed effectiveness. The deep insight into the HILS testbed is presented here. The available delay compensation methods were studied, and a suitable compensation method was implemented. The adverse effectiveness of delay compensation was also discussed.
DISCLOSURE STATEMENT
No potential conflict of interest was reported by the author(s).
Additional information
Notes on contributors
LAV Sanhith Rao
Sanhith Rao LAV, is presently working as Scientist in RCI/DRDO, Hyderabad India, and pursuing PhD from NIT,Warangal. His main area of research is hardware in-loop simulation (HILS) of aerospace systems.
P. Sreehari Rao
Sriharirao Patri received his PhD from NIT,Warangal. Presently, he is working as associate professor in NIT, Warangal. His research interest include mixedsignal IC design in VLSI. Email: [email protected]
I. M. Chhabra
Chhabra IM is presently working as Scientist in RCI/DRDO, Hyderabad, India. His main area of research is developing sensor systems for aerospace vehicles. Email: [email protected]
L. Sobhan Kumar
Sobhan Kumar L is presently working as senior scientist in RCI/DRDO, Hyderabad, India. His main area of research is hardware in-loop simulation (HILS) of aerospace systems. Email: [email protected]