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Abstract
This paper introduces a design methodology that reduces the fundamental trade-off between linearity and power added efficiency (PAE) in CMOS power amplifier (PA). In our work, a stacked power block (SPB) has been proposed to mitigate the effect of gate–source capacitance (Cgs), thus linearizing the PA. Each stage is biased independently to shape the gain profile, either to be in the expanded mode or in the compressed mode, in which once combined it delivers a flat gain response and confirming the linearity performance. Efficient PI input and output matching networks are proposed to ensure no further distortion, once connected to the 50 Ω source and load. The PA achieves input and output return losses of less than −10 dB from 2.40 to 2.50 GHz. At the center frequency of 2.45 GHz, the SPB-PA achieves a gain of 10 dB and it is unconditionally stable. The proposed gain shaping linearization technique delivers a maximum linear output power (Poutlinmax) of 19.8 dBm with only 3.3 dB back-off from maximum output power (Poutmax) of 23.1 dBm. The SPB-PA meets the WLAN specification with linear PAE of 30% and peak PAE of 36.1%. The proposed SPB-PA reduces the fundamental trade-off between linearity and efficiency. Integration of this PA in wireless SoC shall reduce the chip’s overall power consumption.
ACKNOWLEDGEMENT
The authors would also like to acknowledge CEDEC USM for the measurement facilities and Silterra Malaysia for the CMOS 180 nm fabrication support.
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Notes on contributors
Premmilaah Gunasegaran
Premmilaah Gunasegaran received her BEng Tech degree (Hons) in industrial electronics from Technical University of Malaysia Melaka (UTeM), Melaka and MSc degree in microelectronic system engineering from Universiti Sains Malaysia (USM) in 2016 and 2018, respectively. She is currently pursuing her PhD degree in microelectronic systems engineering from Universiti Sains Malaysia (USM), Pulau Pinang. Her research interest includes CMOS RFIC working mainly on power amplifiers and up-mixers for wireless communication system, internet of things (IoT), internet of everything (IoE), and 5G new radio sub-6 GHz applications. Email: [email protected]
Jagadheswaran Rajendran
Jagadheswaran Rajendran (SM’16) is currently serving as senior lecturer at Collaborative Microelectronic Design Excellence Centre (CEDEC) and School of Electrical and Electronic Engineering, Universiti Sains Malaysia, working on CMOS analog IC design, CMOS radio frequency (RF) IC design and monolithic microwave integrated circuit design. He received his BEng (Hons) from Universiti Sains Malaysia in 2004, MEng (Telecommunication) from Multimedia University in 2011, and PhD in RFIC design from the University of Malaya in 2015. He was with Laird Technologies as antenna designer, followed by serving Motorola Technology from 2005 to 2007 as an R&D Engineer, working on a mobile phone receiver system. In 2008, Dr Jaga joined BroadComm as an MMIC designer, working mainly on GaAs-based power amplifier, LNA, and gain blocks. He was elevated to the rank of principal engineer later. In 2015, he joined Silterra Malaysia, working on CMOS RFIC design and device modeling. He has published more than 30 research papers, mainly journals, and holds one US patent and one international patent. Dr Jagadheswaran was the recipient of the IEEE Circuit and System Outstanding Doctoral Dissertation Award in 2015. He served as the Chairman of IEEE ED /MTT/SSC Penang Chapter in 2011 and 2018. He is also a senior member of IEEE.
Selvakumar Mariappan
Selvakumar Mariappan received his BEng Tech degree (Hons) in electrical engineering technology from Technical University of Malaysia Melaka (UTeM) in 2017. He is currently pursuing his PhD degree in microelectronics system engineering from Universiti Sains Malaysia (USM). He was a scholarship recipient of the Industry Graduate Research Assistant Scholarship Programme (i-GRASP) from CREST R&D, Malaysia, and assigned as a postgraduate intern in Silterra (M) Sdn Bhd from 2018 to 2021 where he was involved in CMOS RFIC design. He is currently with QRF Solutions Sdn Bhd as an IC designer and working on RFIC design projects for wireless communication. Email: [email protected]
Sofiyah Sal Hamid
Sofiyah Sal Hamid was born in Penang, Malaysia. She received her BEng degree with honors in electronic engineering in 2012 and an MSc degree of electronic engineering in 2018 from Universiti Sains Malaysia (USM), Malaysia, respectively. In 2014, she joined Intel Microelectronic Malaysia as Analog RF Engineer. In 2015, she joined Collaborative Microelectronic Design Excellence Centre (CEDEC), USM, as research officer in RF analog IC design. Her main research interest includes CMOS RF IC design in wireless and mobile application. Email: [email protected]
Narendra Kumar
Narendra Kumar received his doctorate in electrical engineering from RWTH Technical University Aachen, Aachen, Germany. He has been with Motorola Solutions since early 1999 as principal staff engineer. He has been visiting professor in Istanbul University since January 2011. Since August 2013, he has been with the Department of Electrical Engineering of University Malaya and serving as associate professor. He holds 3 US patents and 4 defensive patents in microwave power amplifiers, all assigned to Motorola Solutions. He has authored more than 80 papers in technical journals and conferences and three technical books published in the USA. He has chaired a few IEEE and PIERS technical conferences in Europe and Asia since 2009. He has been keynote speaker at several IEEE conferences since 2010 (Cyprus, Florida US, Beirut, Bangkok, etc.). Since June 2009, he has been serving as reviewer of IEEE Transactions on Microwave Theory Techniques, IET Circuits, Devices and Systems, etc. He is Senior Member of the Institute of Electrical Electronics Engineers (USA) and a Fellow of the Institution of Engineering Technology (UK). He has been appointed as IEEE Industry Relations Team of Asia Pacific since January 2015 to support industrial linkage activities. Email: [email protected]