An Improved Performance of Gate All-Around Junctionless FET Using Core–Shell Architecture

Abstract

A proposed core–shell gate all-around junctionless field-effect transistor (CS GAA JLFET) is studied using extensive simulations. An oppositely doped core is sandwiched between the shells to achieve lesser leakage current due to an increase in tunneling width at the channel/drain interface and an increase in source/channel barrier height. The core doping is initially optimized, followed by the variation of channel length. Different gate dielectric is studied and investigated. The best performance parameters are obtained for channel length 20 nm with k = 15. The OFF current of ∼10⁻¹⁶ A/µm, ON current of ∼10⁻⁴ A/µm, ON/OFF current ratio ∼10¹², subthreshold slope of 60.61 mV/decade, and drain-induced barrier lowering of 8.5 mV/V are obtained. The study is done using contour plots, surface potential, and central potential to better understand the proposed CS GAA JLFET device. The better control over the carriers in GAA configuration and the advantage of core–shell architecture helps achieve significant improvement in performance parameters.

KEYWORDS:

• Core–shell architecture
• Gate all-around
• Junctionless
• MOSFET
• Short channel effects
• TCAD

DISCLOSURE STATEMENT

No potential conflict of interest was reported by the author(s).

Additional information

Notes on contributors

Vanita Mehta

Vanita Mehta is working as assistant professor in Vaish College of Engineering, Rohtak, India. She has more than 13 years of experience in teaching. She obtained her Bachelor’s in Technology from Kurukshetra University in 2004 and a master’s from Vaish College of Engineering, Rohtak, in 2007. Currently, she is doing her PhD in Guru Jambheshwar University of Science and Technology. Her research interests include device modeling and simulation of MOSFETs.

Sandeep Kumar Arya

Sandeep Kumar Arya received his BTech, MTech, and PhD degrees from the Department of Electronics Communication and Computer Engineering, Regional Engineering College, NIT, Kurukshetra, in 1991, 1993 and 2008, respectively. Currently, he is working as professor in the Department of ECE GJUS&T Hisar. Earlier, he had been chairperson of the Department of ECE GJUS&T Hisar, India, from October 2004 to October 2015. He has more than 21 years of teaching and research experience and more than 80 research papers published/presented in various national/international journals and conferences. His present area of research includes nonlinearities, dispersion compensation for linear and nonlinear optical systems, radio over fiber, and VLSI design. Email: [email protected]

Rajiv Sharma

Rajiv Sharma was born in 1970 at district Rohtak, Haryana, India. He received his Bachelor of Engineering degree in electronics from Dr Babasaheb Ambedkar Marathwada University, Aurangabad, Maharashtra, India in the year 1993. He obtained his Master of Technology degree in electronics and communication engineering from Malviya National Institute of Technology, Jaipur, India in 2004 and PhD (Electronics & Communication Engineering) degree from Guru Gobind Singh Indraprastha University, Delhi, India in 2013. He is presently working as deputy director, professor & head in Electronics and Communication Engineering Department at Bhagwan Parshuram Institute of Technology Delhi, India. He has a teaching experience of 27 years. He has published more than 70 research papers in the international/national journals/conferences. His current research interests include the modeling, analysis and characterization of SOI MOSFETs. Email: [email protected]