Asynchronous Wrapper-Based Low-Power GALS Structural QDMA

Abstract

The design of System-on-Chip systems using synchronous circuits involves complex clock distribution strategies, which envisage challenges for designers to integrate large-scale systems. Globally Asynchronous Locally Synchronous architectures containing asynchronous port controllers encapsulated in the self-timed wrapper have been adopted in this work. These port controllers communicate through Asynchronous Finite State Machines defined by Signal Transition Graphs are implemented adopting the C element. This GALS architecture implemented for the point-to-point interface can also be modified for the multipoint interface. The proposed methodology uses a two-phase handshake protocol to communicate between two Locally Synchronous modules as it has fewer signal transitions, which, in turn, reduces latency. In this paper, the Queue Direct Memory Access subsystem is implemented using the Vivado simulator on UltraScale+™ device at a maximum frequency of 257.4MHz, and various parameters are reported. A comparison shows that the proposed wrapper has improved latency time of 53%, with a reduction in power dissipated by 27% and an increase in gate count by 13%.

KEYWORDS:

• Asynchronous wrapper
• Globally asynchronous locally synchronous
• Handshake protocol
• Muller C element
• Port controller
• Signal transition graphs
• Synthesis logic

DISCLOSURE STATEMENT

No potential conflict of interest was reported by the author(s).

Additional information

Notes on contributors

B.K. Vinay

B K Vinay has a bachelor's degree in electronics and communication engineering and Master's in signal processing & VLSI design. He has more than 7 years of teaching and industry experience. Currently he is pursuing his PhD in VLSI design. Some of his projects have been funded by the Department of Science & Technology Government of India, Karnataka State Council for Science and Technology. His research interest includes low power VLSI design, analog and mixed signal VLSI design, circuit design and simulations, DSP and embedded systems design.

S. Pushpa Mala

S Pushpa Mala has completed her PhD in Jain University, Bangalore. Her research interests include image processing, signal processing and very large-scale integrated systems. Some of her projects have been funded by Karnataka State Council for Science and Technology. She has published around 30 papers in various indexed international journals and conferences. She is a SMIEE. Corresponding author. Email: [email protected]

S. Deekshitha

S Deekshitha is an undergraduate student in the Department of Electronics and Communication Engineering from CMRIT, Visvesvaraya Technological University. Her research interest includes VLSI design. Email: [email protected]