Performance Investigation of a Modified Hybrid Parallel Prefix Adder for Speedy and Lesser Power Computations

Abstract

Achieving high speed and lesser power in large operand adders is greatly necessitated for incorporating modern portable systems, which are highly demanded in the artificial intelligence sector, especially in deep learning-based applications. Conventional speedy adder structures are based on parallel-prefix (PP) types that have huge power consumption. The modified design is deemed the key solution for contemporary demands in today's modern consumer electronics. The existing hybrid adder (HA) architecture functions on the basis of the framework, in which the least significant carriers are produced in large PP adders quicker than the most-significant ones. The base concept of this HA is to customize the binary to Excess-1 Converter (BEC) and make C_in = 1 in the standard Carry Select Adder (CSA) to reduce power and area than RCA. The key improvement in BEC is minimizing the logic gate counts that are necessitated than FA of n-bit architecture. In the existing KS-RCA, the customized BEC is introduced for achieving considerable performance metrics improvement. All existing work and the proposed adder implementation are done in Cadence tool RTL compiler with 90 nm TSMC technologies using the dynamic power verification and analysis methods of RTL. The proposed technique efficiently diminishes the delay that is 76.39% lesser than the CSEL-BEC , 70.86% lesser than CSEL-RCA, and significantly 3.27% lower than the KS-RCA. Also, power consumption is reduced up to 28.92%, 10.61%, and 11.06% than the existing methods, such as KS-RCA, CSEL-RCA, and CSEL-BEC, respectively. However, the area is efficiently reduced by the proposed method up to 29.52% concerning the maximum value of implemented techniques.

KEYWORDS:

• BEC-adder
• Carry select-BEC, Carry skip adder
• Full adder
• Hybrid parallel prefix adder
• Kogge stone adder
• KS-ripply carry adder

ACKNOWLEDGEMENTS

This proposed model work was carried over in research laboratory of SKCET under the guidelines of Dr. C. Ganeshbabu.

Disclosure statement

The authors give full consent to participate in this research work. The authors give full consent for publication of this research work.This manuscript work was solely done by the author Dinesh Kumar J R under the guidelines of the supervisor Dr. C. Ganeshbabu and no funding resources were involved. The author declared there is no potential conflicts of interest involve in this research work and declared this researchwork is not conducted on human participants and or animals.

Additional information

Notes on contributors

J. R. Dinesh Kumar

J R Dinesh Kumar, currently working as assistant professor in Sri Krishna College of Engineering and Technology, Coimbatore and his area of research focuses on VLSI, arithmetic circuit optimization, signal processing and circuits. He is having 8 years of experience in teaching and research and has attended more than 25 international conferences and published 37 papers in reputed Scopus indexed journals. He is life time Member of ISTE and IYANG. He is associated with various research activities of the department and also he is one of the key holders who obtained the fund from ISRO for conducting national level conferences. He is a certified engineer in VHDL, python and blockchain.

C. Ganesh Babu

C Ganesh Babu, currently working as professor, ECE and head/E&I, in Bannari Amman Institute of Technology, Sathyamangalm. He is having experience of more than 22 years in research and teaching and published more than 80 papers in H-indexed journals. Guiding 6 scholars under Anna University and also 4 scholars obtained their doctorate degree under his supervision. His areas of interest are signal processing, VLSI in medical electronics, and digital design and speech signal processing. He obtained research funding for conducting conferences and workshops at the national level and received R&D funds from various governing bodies of India. Also, he is one of the notable reviewers in the journals like JSIR, ETRI, and JIRAS. He is holding lifetime membership in IEEE.Email: [email protected].