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Abstract
This paper reports a PMOS-NMOS Complementary LC voltage-biased oscillator with dual-second harmonic filtering tanks. It features 2 LC networks integrated each at the head and tail of the oscillator to concurrently resonate at twice the oscillating frequency (fLO), forming two high-impedance paths to prevent the PMOS and NMOS –gm differential pairs from loading the main LC resonator when the transistors are driven into the triode region. This improves the voltage and current efficiency of the oscillator. Furthermore, the gate-to-source voltages of the two –gm differential pairs are reshaped to reduce their phase noise contributions. Simulated in 65 nm CMOS, the proposed oscillator with 4.64–5.64 GHz (17.68%) tunability exhibits a power consumption ranging 585.9–655.4 µW while offering a phase noise performance of −139–141.5 dBc/Hz at the 10 MHz offset. The corresponding FoM is 196.2–196.7 dBc/Hz.
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No potential conflict of interest was reported by the author(s).
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Notes on contributors
Mikki How-Wen Loo
Mikki How-Wen Loo was born in Kedah, Malaysia. He received the BE degree (Hons) in electrical and electronic engineering from the Asia Pacific University of Technology and Innovation, Kuala Lumpur, in 2021. He is currently pursuing MSc degree with the Department of Electrical Engineering, University of Malaya, Kuala Lumpur, Malaysia. His main research interest includes CMOS analog-integrated circuits and systems for wireless applications. Email: [email protected]
Harikrishnan Ramiah
Harikrishnan Ramiah received the B Eng (Hons), MSc, and PhD degrees in electrical and electronic engineering, in the field of analog and digital IC design, from the Universiti Sains Malaysia, Penang, Malaysia, in 2000, 2003, and 2008, respectively. In 2002, he was with Intel Technology, Sdn. Bhd, Penang, performing high frequency signal integrity analysis. In 2003, he was with Sires- Labs Sdn. Bhd, Cyberjaya. He is currently a professor with the Department of Electrical Engineering, University of Malaya, Kuala Lumpur, Malaysia, working in the area of RF integrated circuits (RFIC) and RF energy harvesting circuit design. He is the director of the Center of Research Industry 4.0 (CRI 4.0) at the University of Malaya. He has authored or co-authored several articles in technical publications. His main research interests include analog-integrated circuit design, RFIC design, VLSI system design, and radio frequency energy harvesting power management module design. Ramiah is a member of the Institute of Electronics, Information, and Communication Engineers. He was a recipient of the Intel Fellowship Grant Award from 2000 to 2008. He received continuous international research funding in recognition of his work, from 2014 to 2021, such as the Motorola Foundation Grant. He is a Chartered Engineer of the Institute of Electrical Technology and a Professional Engineer registered under the Board of Engineers Malaysia.
Chee Cheow Lim
Chee Cheow Lim was born in Kuala Lumpur, Malaysia. He received his B Eng (Hons) degree in electrical and electronic engineering from the Asia Pacific University of Technology & Innovation (APU), Malaysia in 2014 and a PhD degree in electrical engineering from the University of Malaya (UM), Malaysia in 2019. From 2021 to 2022, he worked as analog engineer at Intel Corporation. He's currently working as a lecturer at APU. His research interests include CMOS RF integrated circuits and systems with a specialization in RF oscillators, modelling, and characterization of passive inductors/transformers. Lim received the best undergraduate final year project award in 2014, IEEE ISSCC 2018 Student Travel Grant Award, and the IEEE SSCS Predoctoral Achievement Award for 2018–2019. Email: [email protected]