Fast and Low-Power CMOS and CNFET based Hysteresis Voltage Comparator

Abstract

This paper presents CMOS and CNFET based hysteresis voltage comparators for low-voltage applications. The proposed CMOS and CNFET hysteresis comparators require merely 1.6 and 0.26 µW of power, respectively, which is less than one tenth of the power dissipated by the other advanced hysteresis comparators designs available in literature. The propagation delay observed in the proposed CMOS and CNFET hysteresis comparators are 162 and 47 ps, respectively, which is almost half the delay exhibited by the other hysteresis comparators. Overall, a 93–99% reduction in Power Delay Product (PDP) can be achieved. Furthermore, the proposed design requires only nine transistors compared to the 11–17 transistor requirement in conventional hysteresis comparators, thus saving up to 47% of chip area.

KEYWORDS:

• 45 nm CMOS technology
• CNFET
• Hysteresis voltage comparator
• Low-power voltage comparator
• Low-voltage comparator
• Power-delay-product

Disclosure statement

No potential conflict of interest was reported by the author(s).

Additional information

Notes on contributors

Abhay S. Vidhyadharan

Abhay S Vidhyadharan is pursuing MTech in automated electrical vehicles from Department of ECE, Mahindra University Ecole Centrale School of Engineering, Hyderabad, Telangana. Earlier, he had completed his BE (ECE) from SRM Institute of Science and Technology, Chennai. His area of interest is digital design with beyond-CMOS technology devices for ultra-lowpower VLSI applications. He specialization includes robotics and IT Network security. He has collaborated with. Sanjay Vidhyadharan at BITS Pilani, Hyderabad Campus for research work on ultra-low-power VLSI designs and has published several papers. E-mail: [email protected]

Gangavarapu Anuhya

Gangavarapu Anuhya completed the BTech in electronics and instrumentation from SASTRA University, Tamilnadu in the year 2019. She is currently pursuing ME microelectronics from BITS Pilani, Hyderabad Campus. Her areas of interest include nano electronic devices and ultra-low-power VLSI circuits. Corresponding author. E-mail: [email protected]

Shivangi Shukla

Shivangi Shukla completed the BE in electronics and telecommunication from Bhilai Institute of Technology, Durg in 2018. She is currently pursuing masters in microelectronics from BITS Pilani, Hyderabad Campus. Her area of interests includes digital design for ultra-low power VLSI applications. E-mail: [email protected]

Sanjay Vidhyadharan

Sanjay Vidhyadharan graduated from Regional Engineering College, Bhopal, in 1994 and was commissioned in Indian Air Force as an engineering officer in the same year. He has immense experience in maintenance of various kinds of helicopters. He obtained MTech in micro electronics and VLSI design from the Indian Institute of Technology, Kharagpur in 2010. He opted for voluntary retirement from Indian Air Force in 2016 to pursue academics. He completed PhD research work on “Novel Gate-Overlap Tunnel FETs and their Circuits for Ultra-Low-Power VLSI applications” in Jan 2020. He is currently working as an assistant professor at BITS Pilani, EEE (WILP) Dept. and his areas of interest is nanoelectronic devices and ultra-low-power VLSI circuits.