Sub-100 nm Ferroelectric-Gate Thin-Film Transistor with Low-Temperature PZT Fabricated on SiO₂/Si Substrate

Abstract

Thin film transistor which uses an active oxide-semiconductor channel and a ferroelectric-gate insulator, so-called FGT, has wide attention for the application of a new nonvolatile memory owing to its prominent features such as simple structure, high speed and low power consumption. Previously, we have reported on demonstration of the FGTs operation, but the ones developed have channel lengths (L_DS) more than 100 nm, which should be reduced for high-density storage in integration circuits. In this work, a new technique has been proposed to fabricate the sub-100 nm FGT using low-temperature PZT thin film, whose source-drain gap would be mainly created from electron beam lithography, dry etching and ashing. With the new technique, the memory functionality of the fabricated sub-100 nm FGTs are comparable with that of the sub-μm sized FGT. In particular, the ON/OFF current ratio is about 10⁴–10⁵, the memory window is 2.0, 1.8 and 1.7 V, and the field-effect mobility is 0.12, 0.07 and 0.16 cm²V⁻¹s⁻¹ for the L_DS of 100, 50, and 30 nm, respectively.

Keywords:

• Electron beam lithography (EBL)
• thin film transistor (TFT)
• ferroelectric
• PZT
• ITO