DL_POLY - A performance overview analysing, understanding and exploiting available HPC technology

ABSTRACT

This paper considers the performance attributes of the molecular simulation code, DL_POLY, as measured and analysed over the past two decades. Following a brief overview of HPC technology, and the performance improvements over that period, we define the benchmark cases – for both DL_POLY Classic and DL_POLY 3 & 4 – used in generating a broad overview of performance across well over 100 HPC systems, from the Cray T3E/1200 to today’s Intel Skylake clusters and accelerator technology offerings from Intel’s Xeon Phi co-processor family. Consideration is given to the tools that have proved helpful in analysing the code’s performance. With a more rigorous analysis of performance on recent systems, we discuss the optimum choice of processor and interconnect, and present power measurements when running the code, comparing these to measurements for other community codes.

KEYWORDS:

• DL_POLY_4
• DL_POLY Classic
• high performance computing
• benchmarking
• molecular dynamics

Disclosure statement

No potential conflict of interest was reported by the authors.

Notes

1 MPI: A Message-Passing Interface Standard. http://www.mpi-forum.org/docs/docs.html, -, 1994.

2 SKU – Stock Keeping Unit. The number of one specific product available for sale. When a hardware device or software package comes in different versions, there is an SKU for each one.

3 https://www.spec.org/cpu2006/.

Additional information

Funding

The work described in sections 5.3 and 5.4 was supported by Engineering and Physical Sciences Research Council: [Grant Number EP/M022617/1]; Intel Corporation: [Grant Number Intel Parallel Computing Centre@Daresbury].