A 7.9–12.1-GHz CMOS LNA employing noise-suppressed and gain-flattened techniques

Abstract

This paper presents the design and implementation of a noise-suppressed and gain-flattened wideband low-noise amplifier (LNA). The noise suppression is achieved by a noise cancelation topology and a body-bias resistor at the input stage. Moreover, the gain flatness is improved by choosing an appropriate coupling coefficient of the transformer at the output. The wideband LNA is fabricated in a standard 0.18-μm CMOS process with a chip size of 0.48 mm². With power consumption of 10.1 mW, the measured results demonstrate power gain of 11.8–13 dB, noise figures of 3.1–4.4 dB, and input/output return losses better than 10 dB from 7.9 to 12.1 GHz. Moreover, the measured input P _1dB and IIP3 is −17.2 and −8.9 dBm, respectively.

Acknowledgements

The authors would like to thank the Chip Implementation Center (CIC), Hsinchu, Taiwan, for chip fabrication and the National Nano Device Laboratories (NDL), Hsinchu, Taiwan, for measurement support.