Experimental investigation of new three phase five level transistor clamped H-bridge inverter

Abstract

This paper presents an experimental investigation of reduced component 3-ɸ, five- level transistor clamped H-bridge (TCHB) voltage source inverter. With reference to review literature, it was found that difficulties were encountered while implementing the developed inverter due the problems in dead band and delay logic. The proposed work in this paper intends to achieve the dead band and delay logic in order to avoid short circuit on DC supply due to simultaneous firing of switches. The inverter is analyzed through MATLAB® SIMULINK software for unity and lagging power factor conditions. The simulation results are verified by means of the practical tests conducted on a laboratory prototype with d-SPACE DS-1103. The performance of inverter is experimentally evaluated for change in the modulation index from 0.5 to 1.2. The importance of deadband and delay logic circuitry for this topology is also explained. THD analysis of output phase voltage and current for the different modulation index is analyzed and realized through experimentation. Finally, comparison of TCHB inverter with classical inverter is given for effectiveness of developed study.

Keywords:

• Transistor clamped H-bridge inverter (TCHB)
• pulse width modulation (PWM)
• THD (Total harmonic distortion)
• multilevel inverter (MLI)
• FFT (Fast Fourier transformation)
• voltage source inverter (VSI)