Profile-guided optimisation for indirect branches in a binary translator

Abstract

Binary translators, which translate the binary executables from one instruction set to another, are useful tools. Indirect branches are one of the key factors that affect the efficiency of binary translators. In the previous research, our lab developed an LLVM-based binary translation framework, called Rabbit. Rabbit introduces novel optimisations: platform-dependent hyperchaining and platform-independent hyperchaining for improving the emulation of the indirect branch instructions. Indirect branch instructions may have several destinations, and these destinations are not known until runtime. Both platform-independent and platform-dependent hyperchaining establish a search table for each indirect branch instruction to record the visited branch destinations at runtime. In this work, we focus on the translation from AArch64 binary to RISC-V binary and further develop the profile-guided optimisation for indirect branch, which collects runtime information, including branch destinations and execution frequency of each destination for each indirect branch instruction, and then use the information to improve hyperchaining (i.e. accelerate the process of finding the branch destination). The profile-guided optimisation can be divided to profile-guided platform-independent hyperchaining and profile-guided platform-dependent hyperchaining. We finally use SPEC CPU 2006 CINT benchmark to evaluate the optimisations. The experiment results indicate that compared with (1) no chaining, (2) platform-independent hyperchaining and (3) platform-dependent hyperchaining, profile-guided platform-independent hyperchaining provides 1.123×, 1.066× and 1.098× speedup respectively. Similarly, profile-guided platform-dependent hyperchaining achieves 1.106×, 1.047× and 1.083× speedup with respect to the above three configurations, respectively.

Keywords:

• Binary translation
• profile-guided optimisation
• hyperchaining
• RISC-V
• AArch64
• LLVM
• rabbit

Disclosure statement

No potential conflict of interest was reported by the author(s).

Notes

1 Our current work focuses RISC-V assembly.

Additional information

Funding

This work was supported by Ministry of Science and Technology, Taiwan, R.O.C., under grant MOST 108-2221-E-009-050-MY3. A preliminary draft of this paper was presented at Workshop of Compiler Techniques for High-Performance Computing (CTHPC) 2021, Taiwan.