Digital Phase Locked Loops

Abstract

The paper describes the phase locked loop (PLL) in detail. Emphasis is on Digital Phase Locked loops (DPLL) and All-Digital Phase Locked Loops (ADPLL). Important parameters of the PLLs are described. Different sub-blocks of DPLL and ADPLL are described and discussed in detail. An example design of ADPLL is also discussed. Digital and All Digital PLLs are gaining popularity because of their ease of implementation in FPGA’s and ASIC’s.

Keywords:

• Phase locked loop
• phase difference
• phase detector
• oscillator
• counter
• S-R Flip-flop
• J-K flip-flop

Additional information

Notes on contributors

Praveen Kumar

Praveen Kumar obtained his B.E. in Electronics and Communication Engineering from Delhi College of Engineering, Delhi, in 1996 and M.E. in Electronics and Communication Engineering from Delhi College of Engineering, Delhi, in 2006. He worked under esteemed guidance of Professor A. Bhattacharyya for final year thesis.

He is currently working as Team Leader in Centre for Development of Telematics (C-DOT), Department of Telecommunication and Information Technology, Govt. of India. He was involved in architecture design and systems design based on “Synchronous Digital Hierarchy”. His expertise is in high speed PCB design and complex FPGA design. He is currently working on development of telecom products based on GPON technology for ‘Fibre to the Home’ applications.