On the Key Schedule of Mini-AES and S-AES Algorithms

Abstract

Mini-AES and S-AES have been proposed in literature to serve as test beds for students and cryptographers. The key schedule generation of both these algorithms can be considered to be based on a non-linear feedback shift register (NFSR). In this paper, we study the key schedule algorithm used in Mini-AES and S-AES regarding two aspects: (a) to know whether any keys of Mini-AES as well as S-AES are weak in the sense that the round keys generated turn out to be same as the actual key (b) to evaluate the period of the sequence generated by the NFSR under various initial conditions. Further, the possibility of deriving the round keys fast as needed in decryption is also explored. Simulation results using C and implementation related evaluation are also presented.

Keywords:

• Cryptography
• AES
• Mini-AES
• S-AES
• key schedule
• data encryption

Additional information

Notes on contributors

Rashmi Ramesh Rachh

Rashmi R. Rachh graduated in Electrical and Electronics Engineering from Karnataka University Dharwad, and completed M.Tech.in Computer Science and Engineering form Manipal Academy of Higher Education, Manipal in 2003. She is currently working towards her Ph.D. under Visvesvaraya Technological University, Belgaum. Her research interests include design of efficient VLSI architectures for cryptosystems and cryptanalysis. Presently, she is working as Asst. Professor in the department of Computer Science and Engineering, KLE Society’s college of engineering and technology, Belgaum.

P.V. Ananda Mohan

Dr. Ananda Mohan obtained his Ph.D degree in Electrical Communication Engineering from Indian Institute of Science, Bangalore in 1975. During 1973–2003, he was with I.T.I. Limited in R&D. Subsequently till 2008, he was with R&D Electronics Corporation of India Limited, Bangalore. He was with N.T.R.O during 2009 and since February 2010, he is with Electronics Corporation of India Limited.

His research interests are in the area of Analog VLSI design, VLSI architectures, Residue Number Systems and Cryptography. He has published in these areas in refereed international journals and conferences. He has published three books Switched Capacitor Filters: Theory, Analysis and Design (Prentice-Hall (London)), Residue Number Systems: Algorithms and Architectures Kluwer Academic Publishers and Current-mode VLSI analog Filters: Design and applications (Birkhauser).

He is a Fellow of IEEE (U.S.A), Fellow IETE (India), Fellow of National Academy of Engineering (India). He was Associate Editor of IEEE Transactions on Circuits and Systems Part I during 2000–2003. He is at present an Associate Editor of Circuits, systems and Signal Processing. He has received the Ram Lai Wadhwa Gold Medal Award from the Institution of Electronics and Telecommunication Engineers (India) in 2003 and Indira Priyadarshini Award in 2004. He has taught at Indian Institute of Science for few years.

B.S. Anami

Dr. Basavaraj S. Anami is presently working as Principal, K. L. E. Institute of Technology. Hubli, Karnataka, India. He completed his Bachelor of Engineering in Electrical Engineering from Karnataka University in the year 1981, M.Tech. in Computer Science from IIT Madras in the year 1986 and received his Ph.D. in Computer Science from University of Mysore in the year 2003. He worked in different capacities, as faculty of Electrical Engineering, professor and head of department of Computer Science and Engineering and Dean in Basaveshwar Engineering College, Bagalkot till 2008. His research interests include Design and development of expert system, Machine learning, Image Processing in Agriculture, Horticulture and Food processing. He has published 50 research papers in peer reviewed International Journals and conferences proceedings. He has guided three candidates for PhD. His two books are published by Prentice Hall India and Wiley India