Ferroelectric nonvolatile logic

Abstract

This paper describes the design of nonvolatile logic elements using ferroelectric materials. Two separate approaches are discussed. The first approach involves shadowing a CMOS latch or flip-flop with a single bit 2T/2C ferroelectric memory. The second approach offers improved density by integrating ferroelectric capacitors within the logic element. Both designs employ non-switching ferroelectric capacitors to establish the optimum bit line load in the absence of sufficient parasitic capacitance. The paper further describes low-voltage and wide-voltage design techniques used to realize 2.7 – 5.5V products on a “5-volt” ferroelectric process. These same techniques allow 1.8V ferroelectric memory products to be designed using the upcoming generation of production ready “3-volt” ferroelectric materials. Layout effects are discussed, as well as bit/cell ratio optimization.

Key Words:

• ferroelectric memory
• nonvolatile logic
• ferroelectric boost