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Abstract
A 1T2C-type ferroelectric memory cell, in which two ferroelectric capacitors with the same area are connected to the gate of an usual MOSFET with a SiO2/Si interface, was fabricated and characterized. It was found that the memory window significantly changed by the device parameters, which means that the low voltage operation is possible if we optimize these parameters. The fabricated cell, is composed of a stacked gate structure of Pt/SBT/Pt/Ti/SiO2/Si with the area ratio of the MOS capacitor to the ferroelectric capacitor of 6 or 10. Nonvolatile memory operation was confirmed, in which the current on/off ratio was larger than 3-order-of magnitude and the data retention time was longer than 6 × 104 seconds.