Single Cell Capacitor Hysteresis Loop Testing on Wafer Level on a 32 MB Chain FeRAM^TM After Full Integration

Abstract

Ferroelectric memory devices are under development for future memory technologies due to their ideal properties. They combine non-volatility with fast read/write access, low power consumption and high density making them useful within telecommunication, portable applications and massive data processing. The reliability of the FeRAM device is mainly determined by weak bit cells, which, for some reason, have a smaller cell charge than the average value. The measurement of ferroelectric properties of the capacitors is performed on cell array like capacitor arrays, which give only averaged results for switching charge, coercive voltage and polarization. Therefore these results can not be used to identify single weak capacitors and their location. This inhibits the analysis of the degradation phenomena on a fine scale. The hysteresis measurement on individual cell capacitors overcomes this gap.

ACKNOWLEDGEMENT

The authors would like to thank J. Rickes for the fruitful discussions of the design modifications and the FeRAM companies for their steady encouragement to develop this test method.