A Novel Chain FRAM with Driven Plate Read Scheme

Abstract

A novel chain ferroelectric random access memory (chain FRAM) is proposed. The memory cell is composed of a transfer gate, a ferroelectric capacitor connected in parallel, and a NMOS transistor. And one memory cellblock consists of plural memory cells connected in serials. Small cell size can be obtained by using this chain FRAM architecture. Low stand-by power consumption contemporaneous with high stability can be realized because of no disturbance during the stand-by cycles. Also it can provide lower voltage operation, higher sensing margin and faster operation without refresh cycles than the conventional one. The voltage drop over transistors can also be decreased dramatically using transfer gates and higher security can be obtained.

Keywords:

• ferroelectric memory
• random access memory (RAM)
• chain FRAM