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Integrated Ferroelectrics
An International Journal
Volume 67, 2004 - Issue 1
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Original Articles

A Graded Sense-Load Scheme and Cell Data Distribution in FeRAM

, , , , &
Pages 245-254 | Received 01 May 2004, Accepted 01 Jul 2004, Published online: 12 Aug 2010
 

Abstract

The graded main-bitline (MBL) sense-load is adopted in the hierarchical bitline structure. The unit cell array block is composed of the cell array of 2 k rows and 128 columns, which is divided into 32 sub_block sections. The sub_block is composed of the cell array of 64 rows and 128 columns. The nine MBL-sense-load (MSL) devices are located in every four sub_block intervals. When one of four sub_blocks is activated, the two MSLs located at the edge of four sub_blocks are activated. The graded size slope target of MSL in 2 k rows cell array is about 20% variation from maximum MSL size. The sensing voltage distribution with graded sense-load is about less than 50 mV. The average sensing voltage with 2Pr value of 5 μ C/cm2 and sub-bitline (SBL) capacitance of 40 fF is about 700 mV at 3.0 V operation voltage. Thus allowed minimum 2Pr value for high density Ferroelectric RAM (FeRAM) can move down to about less than 5 μ C/cm2.

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