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Abstract
In this paper, we analyze the radio frequency (RF) performance for novel junctionless vertical MOSFETs (JLVMOS) with different thicknesses of silicon pillar (T Si = 5, 10 nm). In addition, a junctionless planar SOI MOSFET is also designed for the comparison in this work. According to the numerical simulations, the JLVMOS of T Si = 5 nm gets the highest in g m and g m/I DS, but the T Si = 10 nm one gets the highest in A VI. Moreover, due to the double-gate (DG) structure of the VMOS, it can increase the gate controllability over the channel region.
Acknowledgment
This work was supported in part by the National Science Council of Taiwan, R.O.C., under Contact No. NSC98-2221-E-110-075. We are grateful to the Taiwan National Center for High-performance Computing for computer time and facilities.