A Novel Vertical MOSFET with bMPI Structure for 1T-DRAM Applications: A 2-D Numerical Study

Cheng-Hsin Chen Dept. of Electrical Engineering, National Sun Yat Sen University, Kaohsiung, 80424, Taiwan, R.O.C

Jyi-Tsong Lin Dept. of Electrical Engineering, National Sun Yat Sen University, Kaohsiung, 80424, Taiwan, R.O.C

Yi-Chuen Eng Dept. of Electrical Engineering, National Sun Yat Sen University, Kaohsiung, 80424, Taiwan, R.O.C

Po-Hsieh Lin Dept. of Electrical Engineering, National Sun Yat Sen University, Kaohsiung, 80424, Taiwan, R.O.C

Hsien-Nan Chiu Dept. of Electrical Engineering, National Sun Yat Sen University, Kaohsiung, 80424, Taiwan, R.O.C

Tzu-Feng Chang Dept. of Electrical Engineering, National Sun Yat Sen University, Kaohsiung, 80424, Taiwan, R.O.C

Abstract

This paper proposes a novel vertical MOSFET with the middle partial insulation and block oxide (bMPI) structure for 1T-DRAM application. The bMPI 1T-DRAM can increase the pseudo-neutral region due to the bMPI under the vertical channel and its device sensing current window is improved about 95% when compared to the planer bMPI 1T-DRAM. Because of the double gate structure, the proposed device has great gate controllability; hence, it can reduce the short-channel effects and enhance the electrical characteristics.

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A Novel Vertical MOSFET with bMPI Structure for 1T-DRAM Applications: A 2-D Numerical Study

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A Novel Vertical MOSFET with bMPI Structure for 1T-DRAM Applications: A 2-D Numerical Study

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