An Influence of Temperature Variation for the DC and RF/Analog Performance in a Novel Dual-Channel Source/Drain-Tied MOSFET

Abstract

In this work, we propose a novel transistor called dual-channel source/drain-tied (DCSDT) MOSFET. The process for producing the device employs the multiple epitaxial growths of SiGe/Si layers and selective SiGe removal to form the block oxide island (BOI) in this work. Due to the source/drain-tied scheme giving more pass way to dissipate generated heat, the both DC and RF/analog performance of the device are not seriously affected according to the numerical simulation results.

Acknowledgments

This work was supported in part by the National Science Council of Taiwan, R.O.C., under Contact No. NSC98-2221-E-110-075. We are grateful to the National Center for High-performance Computing for computer time and facilities.