Abstract
The imprint mechanism in ferroelectric capacitors was reported in 1992 by National Semiconductor. In retrospect, that mechanism was visible in the very first memories fabricated at Krysalis Corporation in 1987 but were not recognized as such. Since 1992, new test procedures have been developed at Radiant Technologies, Inc. that clearly delineate the physical nature of solid state imprint in ferroelectric memories and how it causes retention loss in CMOS memory IC's. Using the test procedures, the failure point in time of the memory IC due to imprint can be pinpointed exactly. A production reliability test can be developed from the procedures. The primary impact of imprint is on the remanent polarization component of the ferroelectric material.