Plasma etch processing of advanced ferroelectric devices

Abstract

Ferroelectric structures are being used in SRAM devices and are migrating to DRAM devices. A DRAM cell size can be dramatically reduced by employing ferroelectric structures in place of the current silicon oxide capacitor structures. A 5μ² DRAM cell capacitor can be reduced in size by a factor of 20 using a ferroelectric structure.

The current technology used to etch ferroelectric device layers has at least two major shortcomings. The first etch issue is the sloped profiles (i.e. 40°) which are a result of the high ion energies used to etch the relatively non volatile materials (Platinum and PZT). The second etch issue is severe sidewall redeposition when vertical profiles are obtained by using ion mills etc. The etch products that are redeposited on the sidewalls become very difficult or impossible to remove in a manufacturing environment. Profiles of > 75° without heavy redeposition will be required in order for 0.5μ DRAMs to be produced using ferroelectric technology.

A series of designed experiments were developed to understand the dependent variables impact on reducing residues and increasing the etched feature's profile angle. Response surfaces were developed for resist selectivity, profile angle, and etch rate versus changes in KHz power, cathode temperature, reactant gas flow and additive gas flow in an HRe ⁻ (High Density Reflected Electron) etch system. The process results (optical emission and SEM analysis) were statistically evaluated and process trends developed. The resulting response surface graphs combined with SEM micrographs demonstrate trends in profile control and etch rate. The process trends are reviewed which result in > 75° residue-free etching of ferroelectric devices.