Optimization of plastic packaging of ferroelectric semiconductor memories

Abstract

As the market for ferroelectric semiconductor memories matures, optimizing the assembly flow of these memories into plastic devices becomes a key consideration in the profitability of a product. In this paper, we will propose an optimized assembly flow that will improve retention yields and product reliability. This new flow reduces the time at elevated temperature which has been known to cause compensation shift of the hysteresis loop and a reduction of ferroelectric switching.

Typically, combined cures during plastic assembly of ferroelectric memories can be as long as 10 hours at temperatures which activate the imprint mechanism as they approach the Curie point. Current processes use ink cures, wafer mount cures, die attach cures, wire bonding, die coat cures, molding, molding cures and, back and top marking cures. We will review a completed analysis that introduces a thermal budget, or a reduction of time at temperature, for four of these process steps; die attach cures, die coat cures, molding cures and marking cures. This work will show that using mold and die coat materials that use low temperature cures improves yields. Additionally, retention yields will improve by a factor of 2.8X when the temperature profile used for curing these materials is also reduced.

Key Words:

• ferroelectric
• retention
• assembly