AN EFFICIENT NETWORK ANALYSER BASED ON LINEAR ARRAY ARCHITECTURE∗

This work has been supported in part by EEC project RACE R1083.

Abstract

In this paper we present an array based network analyzer for Broadband Integrated Services Digital Networks. The analyzer is laid as a linear array processor. We describe the implementation of the analyzer's functions on the array processor. Apart the real-time application, the importance of this study becomes more apparent by the fact that, the resulting design can be implemented on configurable gate array and be attached to a microprocessor. Nevertheless, it is also possible to use the analyser array in combination with commercially available hardware to debug the network equipment in the development phase.

KEY WORDS:

• Linear arrays
• string matching
• broadband networks
• network analyzer

Notes

This work has been supported in part by EEC project RACE R1083.