Verification of algorithm for automatic detection of electronic devices mounted on waste printed circuit boards

ABSTRACT

In this study, an algorithm for sorting waste products that is capable of automatically determining the value of raw materials during the sorting process is proposed. The algorithm automatically measures the sum of the top surface areas of integrated circuits (ICs), memory assemblies, and connectors (which account for over 80% of the resource value) from two-dimensional (2D) digital images of waste printed circuit boards. The sum of top surface areas is directly correlated with the total resource value. This algorithm continuously identifies the characteristics (e.g., color, size, and shape) of each device and performs relatively simple sequences of image processing. Tests on 46 types of waste digital-camera boards reveal the detection rates for ICs/memories and connectors to be 73% and 86%, respectively. The first measure is low because ICs/memories with long-side lengths of 2–5 mm are incorrectly identified as transistors or diodes in several cases. However, the proportion of ICs and memories with sides ≥5 mm is determined to be approximately 90% based on the sum of top surface areas, and the estimated values are 105% and 95% of the measured values, respectively. Furthermore, the sum of the top surface areas of both ICs and connectors is 101%. This reveals that the resource values can be estimated with a certain degree of accuracy. The analysis of cases of false detection and non-detection enable the identification of the major factors causing non-identification. The use of machine learning algorithms is determined to be an effective countermeasure. Furthermore, mitigation methods are specified.

Implications: An automatic detection algorism of electric devices mounted on waste printed circuit boards was constructed to straightforwardly and rapidly evaluate the resource values of printed circuit boards in small waste home appliances. A program developed based on the algorithm automatically measures the sum of the top surface areas of ICs/memory and connectors, which account for over 80% of the resource value of mounted devices. Because the structure of the algorithm is simple and can be applied to multiple target devices, high-speed processing can be achieved when implementing a waste product sorter.

Acknowledgment

This study is based on results obtained in a project (code: P17001) commissioned by the New Energy and Industrial Technology Development Organization (NEDO).

Data availability

The authors confirm that the data supporting the findings of this study are available within the article.

Disclosure statement

No potential conflict of interest was reported by the author(s).

Additional information

Funding

This work was supported by the New Energy and Industrial Technology Development Organization [P17001].

Notes on contributors

Naohito Hayashi

Naohito Hayashi is a leader of Resource Value Creations Research Group, Environmental Management Research Institute, National Institute of Advanced Industrial Science and Technology (AIST).

Shigeki Koyanaka

Shigeki Koyanaka is a chief senior researcher of Resource Value Creations Research Group, Environmental Management Research Institute, AIST.

Tatsuya Oki

Tatsuya Oki is a deputy director of Environmental Management Research Institute, AIST.