Frequency and phase-locked loops using adaptive phase detectors

Abstract

Three adaptive frequency and phase-locked loops (referred as APLL, APLL1, and APLL2) are presented that uses a modified phase detector for improved performance. These adaptive phase-locked loops (PLL) have considerably superior performance compared to the conventional and Costas PLL in terms of convergence speed, tracking quality, and frequency acquisition range as well as acquisition time under dynamic conditions. The stability and convergence properties of these three adaptive PLLs are studied using Lyapunov methods. Further, the influence of the design parameters on the tracking and noise performance of these PLLs are shown. Unlike conventional PLL, these adaptive PLL have lesser phase and frequency variance and provides smooth estimates of the frequency, phase, and magnitude of the input sinusoid signal. They are also computationally less expensive than the conventional and Costas PLL as there is no need for an additional low pass filter after the multiplier phase detector. Extensive computer simulations are performed to compare and demonstrate their effectiveness for different conditions. Simulation results show that all the three adaptive PLLs outperform conventional and Costas PLL in terms of frequency estimate accuracy and frequency acquisition range. In addition, it is observed from the simulation results that APPL2 has better performance compared the other PLLs in terms of tracking speed, accuracy, and frequency range.

Key Words:

• Phase-locked loops (PLL)
• adaptive PLL
• Predictor Error Based Estimator

Additional information

Notes on contributors

S Sarma

Santanu Sarma

Santanu Sarma received his bachelor degree in electrical engineering from Tripura Engineering College (now National Institute of Technology, Tripura) in 1999 and his MTech in Electronics and Communication Engineering from Indian Institute of Technology Guwahati (IITG) in 2002.

Since 2002, he has been with the Control System Group of ISRO Satellite Centre as a researcher. He has been involved in design and development of Attitude & Orbit Control System, ASIC based design of Business Management Unit (BMU) for INSAT and IRS class of satellites, UML modelling of large software systems, and DSP based system design. His research interests include modeling and analysis of control systems, embedded computing systems, and VLSI signal processing.

He has been the recipient of the national talent scholarship, GATE scholarship, and the winner of the gold medal of Tripura University. He is a member of IEEE and IETE, India.