Power Aware Channel Width Tapering of Serially Connected MOSFETs

Abstract

In this paper a new transistor channel width tapering scheme called hill tapering for FET chains is proposed with specific emphasis on power dissipation and layout area of the tapered chains. This tapering scheme results in the lowest power dissipation and physical area compared to any of the existing tapering schemes, like linear, exponential or optimal tapering. It also offers high speed operation. The proposed scheme is general and can be used in all domino logic circuit designs. SPICE simulation results have shown that up to 81% power dissipation reduction could be achieved by using the proposed tapering scheme.

Key Words:

• Elmore delay
• power dissipation
• transistor sizing
• transistor tapering

Additional information

Notes on contributors

S. Choudhary

Sudhanshu Choudhary was born in Lucknow, India. He received his Bachelor’s degree in Electronics and Communication Engineering from Birla Institute of Technology, MESRA Ranchi, India, in 2002 and his Master’s degree from Indian Institute of Information Technology & Management Gwalior, India, in 2006. At present he is doing his PhD in the Department of Electrical Engineering at IIT Kanpur. His research interests include microelectronics, VLSI testing and physical design.

S. Qureshi

Prof Shafi Qureshi was born in Srinagar, India. He received his Bachelor’s degree in Electrical Engineering from University of Kashmir in 1974 and his PhD degree from University of California, Berkeley, in 1991. He joined IIT Kanpur in 1992 and became professor in the Department of Electrical Engineering in 1997. His research interests include semiconductor device physics and modeling, thin film transistors, and VLSI design. He is senior member of IEEE and fellow of the Institution of Electronics and Telecommunication Engineers (IETE) India.